simple-atomic-mp-ruby.py revision 8801
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26166Ssteve.reinhardt@amd.com# All rights reserved. 36166Ssteve.reinhardt@amd.com# 46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 136166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 146166Ssteve.reinhardt@amd.com# 156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266166Ssteve.reinhardt@amd.com# 276166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski 286166Ssteve.reinhardt@amd.com 296166Ssteve.reinhardt@amd.comimport m5 306166Ssteve.reinhardt@amd.comfrom m5.objects import * 316166Ssteve.reinhardt@amd.com 326166Ssteve.reinhardt@amd.com 336166Ssteve.reinhardt@amd.comnb_cores = 4 346166Ssteve.reinhardt@amd.comcpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 356166Ssteve.reinhardt@amd.com 366289Snate@binkert.orgimport ruby_config 376870Sdrh5@cs.wisc.eduruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 386289Snate@binkert.org 396166Ssteve.reinhardt@amd.com# system simulated 406289Snate@binkert.orgsystem = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 416166Ssteve.reinhardt@amd.com 426166Ssteve.reinhardt@amd.com# add L1 caches 436166Ssteve.reinhardt@amd.comfor cpu in cpus: 447876Sgblack@eecs.umich.edu cpu.connectAllPorts(system.membus) 456166Ssteve.reinhardt@amd.com cpu.clock = '2GHz' 466166Ssteve.reinhardt@amd.com 476166Ssteve.reinhardt@amd.com# connect memory to membus 486166Ssteve.reinhardt@amd.comsystem.physmem.port = system.membus.port 496166Ssteve.reinhardt@amd.com 506166Ssteve.reinhardt@amd.com 516166Ssteve.reinhardt@amd.com# ----------------------- 526166Ssteve.reinhardt@amd.com# run simulation 536166Ssteve.reinhardt@amd.com# ----------------------- 546166Ssteve.reinhardt@amd.com 558801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 566166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'atomic' 57