pc-simple-timing-ruby.py revision 9793
1695SN/A# Copyright (c) 2012 Mark D. Hill and David A. Wood 29262Ssascha.bischoff@arm.com# All rights reserved. 39262Ssascha.bischoff@arm.com# 49262Ssascha.bischoff@arm.com# Redistribution and use in source and binary forms, with or without 59262Ssascha.bischoff@arm.com# modification, are permitted provided that the following conditions are 69262Ssascha.bischoff@arm.com# met: redistributions of source code must retain the above copyright 79262Ssascha.bischoff@arm.com# notice, this list of conditions and the following disclaimer; 89262Ssascha.bischoff@arm.com# redistributions in binary form must reproduce the above copyright 99262Ssascha.bischoff@arm.com# notice, this list of conditions and the following disclaimer in the 109262Ssascha.bischoff@arm.com# documentation and/or other materials provided with the distribution; 119262Ssascha.bischoff@arm.com# neither the name of the copyright holders nor the names of its 129262Ssascha.bischoff@arm.com# contributors may be used to endorse or promote products derived from 139262Ssascha.bischoff@arm.com# this software without specific prior written permission. 141762SN/A# 15695SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16695SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17695SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18695SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19695SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20695SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21695SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22695SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23695SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24695SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25695SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26695SN/A# 27695SN/A# Authors: Nilay Vaish 28695SN/A 29695SN/Aimport m5, os, optparse, sys 30695SN/Afrom m5.objects import * 31695SN/Am5.util.addToPath('../configs/common') 32695SN/Afrom Benchmarks import SysConfig 33695SN/Aimport FSConfig 34695SN/A 35695SN/Am5.util.addToPath('../configs/ruby') 36695SN/Am5.util.addToPath('../configs/topologies') 37695SN/Aimport Ruby 38695SN/Aimport Options 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edu# Add the ruby specific and protocol specific options 419262Ssascha.bischoff@arm.comparser = optparse.OptionParser() 42695SN/AOptions.addCommonOptions(parser) 43695SN/ARuby.define_options(parser) 44695SN/A(options, args) = parser.parse_args() 45695SN/A 46695SN/A# Set the default cache size and associativity to be very small to encourage 47729SN/A# races between requests and writebacks. 48695SN/Aoptions.l1d_size="32kB" 494078Sbinkertn@umich.eduoptions.l1i_size="32kB" 509262Ssascha.bischoff@arm.comoptions.l2_size="4MB" 519262Ssascha.bischoff@arm.comoptions.l1d_assoc=2 529262Ssascha.bischoff@arm.comoptions.l1i_assoc=2 539262Ssascha.bischoff@arm.comoptions.l2_assoc=2 549262Ssascha.bischoff@arm.comoptions.num_cpus = 2 559262Ssascha.bischoff@arm.com 569262Ssascha.bischoff@arm.com#the system 579262Ssascha.bischoff@arm.commdesc = SysConfig(disk = 'linux-x86.img') 589262Ssascha.bischoff@arm.comsystem = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus, 599262Ssascha.bischoff@arm.com mdesc=mdesc, Ruby=True, 609262Ssascha.bischoff@arm.com 619262Ssascha.bischoff@arm.comsystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 629262Ssascha.bischoff@arm.comsystem.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] 639262Ssascha.bischoff@arm.com 649262Ssascha.bischoff@arm.comRuby.create_system(options, system, system.piobus, system._dma_ports) 659262Ssascha.bischoff@arm.com 669262Ssascha.bischoff@arm.com# Create a seperate clock domain for Ruby 679262Ssascha.bischoff@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 687823Ssteve.reinhardt@amd.com 697822Ssteve.reinhardt@amd.comfor (i, cpu) in enumerate(system.cpu): 70695SN/A # create the interrupt controller 719262Ssascha.bischoff@arm.com cpu.createInterruptController() 729262Ssascha.bischoff@arm.com # Tie the cpu ports to the correct ruby system ports 739262Ssascha.bischoff@arm.com cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 749262Ssascha.bischoff@arm.com cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 759262Ssascha.bischoff@arm.com cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 769262Ssascha.bischoff@arm.com cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 779262Ssascha.bischoff@arm.com cpu.interrupts.pio = system.piobus.master 787811Ssteve.reinhardt@amd.com cpu.interrupts.int_master = system.piobus.slave 79695SN/A cpu.interrupts.int_slave = system.piobus.master 80695SN/A 81 # Set access_phys_mem to True for ruby port 82 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 83 84root = Root(full_system = True, system = system) 85m5.ticks.setGlobalFrequency('1THz') 86