pc-simple-timing-ruby.py revision 9793
11196Shsul@eecs.umich.edu# Copyright (c) 2012 Mark D. Hill and David A. Wood 21196Shsul@eecs.umich.edu# All rights reserved. 31196Shsul@eecs.umich.edu# 41196Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 51196Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 61196Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 71196Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 81196Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 91196Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 101196Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 111196Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 121196Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 131362Shsul@eecs.umich.edu# this software without specific prior written permission. 141648Sbinkertn@umich.edu# 151196Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161196Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171196Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181196Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191196Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201196Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211196Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221196Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231196Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241196Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251196Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261196Shsul@eecs.umich.edu# 271645Srdreslin@umich.edu# Authors: Nilay Vaish 281645Srdreslin@umich.edu 291196Shsul@eecs.umich.eduimport m5, os, optparse, sys 301196Shsul@eecs.umich.edufrom m5.objects import * 311196Shsul@eecs.umich.edum5.util.addToPath('../configs/common') 321196Shsul@eecs.umich.edufrom Benchmarks import SysConfig 331196Shsul@eecs.umich.eduimport FSConfig 341196Shsul@eecs.umich.edu 351196Shsul@eecs.umich.edum5.util.addToPath('../configs/ruby') 361196Shsul@eecs.umich.edum5.util.addToPath('../configs/topologies') 371196Shsul@eecs.umich.eduimport Ruby 381196Shsul@eecs.umich.eduimport Options 391196Shsul@eecs.umich.edu 401196Shsul@eecs.umich.edu# Add the ruby specific and protocol specific options 411196Shsul@eecs.umich.eduparser = optparse.OptionParser() 421196Shsul@eecs.umich.eduOptions.addCommonOptions(parser) 431196Shsul@eecs.umich.eduRuby.define_options(parser) 441196Shsul@eecs.umich.edu(options, args) = parser.parse_args() 451196Shsul@eecs.umich.edu 461196Shsul@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 471196Shsul@eecs.umich.edu# races between requests and writebacks. 481196Shsul@eecs.umich.eduoptions.l1d_size="32kB" 491196Shsul@eecs.umich.eduoptions.l1i_size="32kB" 501196Shsul@eecs.umich.eduoptions.l2_size="4MB" 511196Shsul@eecs.umich.eduoptions.l1d_assoc=2 521648Sbinkertn@umich.eduoptions.l1i_assoc=2 531196Shsul@eecs.umich.eduoptions.l2_assoc=2 541196Shsul@eecs.umich.eduoptions.num_cpus = 2 551196Shsul@eecs.umich.edu 561196Shsul@eecs.umich.edu#the system 57mdesc = SysConfig(disk = 'linux-x86.img') 58system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus, 59 mdesc=mdesc, Ruby=True, 60 61system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') 62system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] 63 64Ruby.create_system(options, system, system.piobus, system._dma_ports) 65 66# Create a seperate clock domain for Ruby 67system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 68 69for (i, cpu) in enumerate(system.cpu): 70 # create the interrupt controller 71 cpu.createInterruptController() 72 # Tie the cpu ports to the correct ruby system ports 73 cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave 74 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave 75 cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave 76 cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave 77 cpu.interrupts.pio = system.piobus.master 78 cpu.interrupts.int_master = system.piobus.slave 79 cpu.interrupts.int_slave = system.piobus.master 80 81 # Set access_phys_mem to True for ruby port 82 system.ruby._cpu_ruby_ports[i].access_phys_mem = True 83 84root = Root(full_system = True, system = system) 85m5.ticks.setGlobalFrequency('1THz') 86