pc-o3-timing.py revision 8451
18451Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 28451Sgblack@eecs.umich.edu# All rights reserved. 38451Sgblack@eecs.umich.edu# 48451Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 58451Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 68451Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 78451Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 88451Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 98451Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 108451Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 118451Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 128451Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 138451Sgblack@eecs.umich.edu# this software without specific prior written permission. 148451Sgblack@eecs.umich.edu# 158451Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 168451Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 178451Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 188451Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 198451Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 208451Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 218451Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 228451Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 238451Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 248451Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 258451Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 268451Sgblack@eecs.umich.edu# 278451Sgblack@eecs.umich.edu# Authors: Steve Reinhardt 288451Sgblack@eecs.umich.edu 298451Sgblack@eecs.umich.eduimport m5 308451Sgblack@eecs.umich.edufrom m5.objects import * 318451Sgblack@eecs.umich.edum5.util.addToPath('../configs/common') 328451Sgblack@eecs.umich.edufrom Benchmarks import SysConfig 338451Sgblack@eecs.umich.eduimport FSConfig 348451Sgblack@eecs.umich.edu 358451Sgblack@eecs.umich.edumem_size = '128MB' 368451Sgblack@eecs.umich.edu 378451Sgblack@eecs.umich.edu# -------------------- 388451Sgblack@eecs.umich.edu# Base L1 Cache 398451Sgblack@eecs.umich.edu# ==================== 408451Sgblack@eecs.umich.edu 418451Sgblack@eecs.umich.educlass L1(BaseCache): 428451Sgblack@eecs.umich.edu latency = '1ns' 438451Sgblack@eecs.umich.edu block_size = 64 448451Sgblack@eecs.umich.edu mshrs = 4 458451Sgblack@eecs.umich.edu tgts_per_mshr = 8 468451Sgblack@eecs.umich.edu is_top_level = True 478451Sgblack@eecs.umich.edu 488451Sgblack@eecs.umich.edu# ---------------------- 498451Sgblack@eecs.umich.edu# Base L2 Cache 508451Sgblack@eecs.umich.edu# ---------------------- 518451Sgblack@eecs.umich.edu 528451Sgblack@eecs.umich.educlass L2(BaseCache): 538451Sgblack@eecs.umich.edu block_size = 64 548451Sgblack@eecs.umich.edu latency = '10ns' 558451Sgblack@eecs.umich.edu mshrs = 92 568451Sgblack@eecs.umich.edu tgts_per_mshr = 16 578451Sgblack@eecs.umich.edu write_buffers = 8 588451Sgblack@eecs.umich.edu 598451Sgblack@eecs.umich.edu# --------------------- 608451Sgblack@eecs.umich.edu# Page table walker cache 618451Sgblack@eecs.umich.edu# --------------------- 628451Sgblack@eecs.umich.educlass PageTableWalkerCache(BaseCache): 638451Sgblack@eecs.umich.edu assoc = 2 648451Sgblack@eecs.umich.edu block_size = 64 658451Sgblack@eecs.umich.edu latency = '1ns' 668451Sgblack@eecs.umich.edu mshrs = 10 678451Sgblack@eecs.umich.edu size = '1kB' 688451Sgblack@eecs.umich.edu tgts_per_mshr = 12 698451Sgblack@eecs.umich.edu 708451Sgblack@eecs.umich.edu# --------------------- 718451Sgblack@eecs.umich.edu# I/O Cache 728451Sgblack@eecs.umich.edu# --------------------- 738451Sgblack@eecs.umich.educlass IOCache(BaseCache): 748451Sgblack@eecs.umich.edu assoc = 8 758451Sgblack@eecs.umich.edu block_size = 64 768451Sgblack@eecs.umich.edu latency = '50ns' 778451Sgblack@eecs.umich.edu mshrs = 20 788451Sgblack@eecs.umich.edu size = '1kB' 798451Sgblack@eecs.umich.edu tgts_per_mshr = 12 808451Sgblack@eecs.umich.edu addr_range = AddrRange(0, size=mem_size) 818451Sgblack@eecs.umich.edu forward_snoops = False 828451Sgblack@eecs.umich.edu 838451Sgblack@eecs.umich.edu#cpu 848451Sgblack@eecs.umich.educpu = DerivO3CPU(cpu_id=0) 858451Sgblack@eecs.umich.edu#the system 868451Sgblack@eecs.umich.edumdesc = SysConfig(disk = 'linux-x86.img') 878451Sgblack@eecs.umich.edusystem = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 888451Sgblack@eecs.umich.edusystem.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 898451Sgblack@eecs.umich.edusystem.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] 908451Sgblack@eecs.umich.edusystem.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] 918451Sgblack@eecs.umich.edusystem.iocache = IOCache(addr_range=mem_size) 928451Sgblack@eecs.umich.edusystem.iocache.cpu_side = system.iobus.port 938451Sgblack@eecs.umich.edusystem.iocache.mem_side = system.membus.port 948451Sgblack@eecs.umich.edu 958451Sgblack@eecs.umich.edusystem.cpu = cpu 968451Sgblack@eecs.umich.edu#create the l1/l2 bus 978451Sgblack@eecs.umich.edusystem.toL2Bus = Bus() 988451Sgblack@eecs.umich.edu 998451Sgblack@eecs.umich.edu#connect up the l2 cache 1008451Sgblack@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 1018451Sgblack@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.port 1028451Sgblack@eecs.umich.edusystem.l2c.mem_side = system.membus.port 1038451Sgblack@eecs.umich.edu 1048451Sgblack@eecs.umich.edu#connect up the cpu and l1s 1058451Sgblack@eecs.umich.educpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 1068451Sgblack@eecs.umich.edu L1(size = '32kB', assoc = 4), 1078451Sgblack@eecs.umich.edu PageTableWalkerCache(), 1088451Sgblack@eecs.umich.edu PageTableWalkerCache()) 1098451Sgblack@eecs.umich.edu# connect cpu level-1 caches to shared level-2 cache 1108451Sgblack@eecs.umich.educpu.connectAllPorts(system.toL2Bus, system.membus) 1118451Sgblack@eecs.umich.educpu.clock = '2GHz' 1128451Sgblack@eecs.umich.edu 1138451Sgblack@eecs.umich.eduroot = Root(system=system) 1148451Sgblack@eecs.umich.edum5.ticks.setGlobalFrequency('1THz') 1158451Sgblack@eecs.umich.edu 116