pc-o3-timing.py revision 8451 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42    latency = '1ns'
43    block_size = 64
44    mshrs = 4
45    tgts_per_mshr = 8
46    is_top_level = True
47
48# ----------------------
49# Base L2 Cache
50# ----------------------
51
52class L2(BaseCache):
53    block_size = 64
54    latency = '10ns'
55    mshrs = 92
56    tgts_per_mshr = 16
57    write_buffers = 8
58
59# ---------------------
60# Page table walker cache
61# ---------------------
62class PageTableWalkerCache(BaseCache):
63    assoc = 2
64    block_size = 64
65    latency = '1ns'
66    mshrs = 10
67    size = '1kB'
68    tgts_per_mshr = 12
69
70# ---------------------
71# I/O Cache
72# ---------------------
73class IOCache(BaseCache):
74    assoc = 8
75    block_size = 64
76    latency = '50ns'
77    mshrs = 20
78    size = '1kB'
79    tgts_per_mshr = 12
80    addr_range = AddrRange(0, size=mem_size)
81    forward_snoops = False
82
83#cpu
84cpu = DerivO3CPU(cpu_id=0)
85#the system
86mdesc = SysConfig(disk = 'linux-x86.img')
87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
89system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)]
90system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)]
91system.iocache = IOCache(addr_range=mem_size)
92system.iocache.cpu_side = system.iobus.port
93system.iocache.mem_side = system.membus.port
94
95system.cpu = cpu
96#create the l1/l2 bus
97system.toL2Bus = Bus()
98
99#connect up the l2 cache
100system.l2c = L2(size='4MB', assoc=8)
101system.l2c.cpu_side = system.toL2Bus.port
102system.l2c.mem_side = system.membus.port
103
104#connect up the cpu and l1s
105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
106                            L1(size = '32kB', assoc = 4),
107                            PageTableWalkerCache(),
108                            PageTableWalkerCache())
109# connect cpu level-1 caches to shared level-2 cache
110cpu.connectAllPorts(system.toL2Bus, system.membus)
111cpu.clock = '2GHz'
112
113root = Root(system=system)
114m5.ticks.setGlobalFrequency('1THz')
115
116