o3-timing-mt.py revision 3096
14484Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
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274484Sbinkertn@umich.edu# Authors: Steve Reinhardt
284484Sbinkertn@umich.edu
294484Sbinkertn@umich.eduimport m5
304484Sbinkertn@umich.edufrom m5.objects import *
314484Sbinkertn@umich.edum5.AddToPath('../configs/common')
324484Sbinkertn@umich.edufrom FullO3Config import *
334484Sbinkertn@umich.edu
344484Sbinkertn@umich.educlass MyCache(BaseCache):
354484Sbinkertn@umich.edu    assoc = 2
364484Sbinkertn@umich.edu    block_size = 64
374484Sbinkertn@umich.edu    latency = 1
384484Sbinkertn@umich.edu    mshrs = 10
394484Sbinkertn@umich.edu    tgts_per_mshr = 5
404484Sbinkertn@umich.edu
414484Sbinkertn@umich.educpu = DetailedO3CPU()
424484Sbinkertn@umich.educpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
434484Sbinkertn@umich.edu                              MyCache(size = '2MB'))
444484Sbinkertn@umich.educpu.mem = cpu.dcache
454484Sbinkertn@umich.edu
464484Sbinkertn@umich.edusystem = System(cpu = cpu,
474484Sbinkertn@umich.edu                physmem = PhysicalMemory(),
484484Sbinkertn@umich.edu                membus = Bus())
494484Sbinkertn@umich.edusystem.physmem.port = system.membus.port
504484Sbinkertn@umich.educpu.connectMemPorts(system.membus)
514484Sbinkertn@umich.edu
524484Sbinkertn@umich.eduroot = Root(system = system)
534484Sbinkertn@umich.edu