o3-timing-mt.py revision 3096
12381SN/A# Copyright (c) 2006 The Regents of The University of Michigan
28853Sandreas.hansson@arm.com# All rights reserved.
38711Sandreas.hansson@arm.com#
48711Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without
58711Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
68711Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
78711Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
88711Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
98711Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
108711Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
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128711Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
138711Sandreas.hansson@arm.com# this software without specific prior written permission.
142381SN/A#
152381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
162381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
172381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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252381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
262381SN/A#
272381SN/A# Authors: Steve Reinhardt
282381SN/A
292381SN/Aimport m5
302381SN/Afrom m5.objects import *
312381SN/Am5.AddToPath('../configs/common')
322381SN/Afrom FullO3Config import *
332381SN/A
342381SN/Aclass MyCache(BaseCache):
352381SN/A    assoc = 2
362381SN/A    block_size = 64
372381SN/A    latency = 1
382381SN/A    mshrs = 10
392665Ssaidi@eecs.umich.edu    tgts_per_mshr = 5
402665Ssaidi@eecs.umich.edu
418853Sandreas.hansson@arm.comcpu = DetailedO3CPU()
428922Swilliam.wang@arm.comcpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
432381SN/A                              MyCache(size = '2MB'))
442381SN/Acpu.mem = cpu.dcache
452381SN/A
462381SN/Asystem = System(cpu = cpu,
478922Swilliam.wang@arm.com                physmem = PhysicalMemory(),
482381SN/A                membus = Bus())
492381SN/Asystem.physmem.port = system.membus.port
502381SN/Acpu.connectMemPorts(system.membus)
512381SN/A
522381SN/Aroot = Root(system = system)
532381SN/A