o3-timing-mp-ruby.py revision 8801:1a84c6a81299
16242Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
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266242Sgblack@eecs.umich.edu#
276242Sgblack@eecs.umich.edu# Authors: Ron Dreslinski
286242Sgblack@eecs.umich.edu
296242Sgblack@eecs.umich.eduimport m5
306242Sgblack@eecs.umich.edufrom m5.objects import *
316242Sgblack@eecs.umich.edum5.util.addToPath('../configs/common')
326242Sgblack@eecs.umich.edu
336242Sgblack@eecs.umich.edunb_cores = 4
346242Sgblack@eecs.umich.educpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
356242Sgblack@eecs.umich.edu
366242Sgblack@eecs.umich.eduimport ruby_config
376242Sgblack@eecs.umich.eduruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
386242Sgblack@eecs.umich.edu
396242Sgblack@eecs.umich.edu# system simulated
406242Sgblack@eecs.umich.edusystem = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
416242Sgblack@eecs.umich.edu
426242Sgblack@eecs.umich.edufor cpu in cpus:
436242Sgblack@eecs.umich.edu    cpu.connectAllPorts(system.membus)
446242Sgblack@eecs.umich.edu    cpu.clock = '2GHz'
456242Sgblack@eecs.umich.edu
466242Sgblack@eecs.umich.edu# connect memory to membus
476242Sgblack@eecs.umich.edusystem.physmem.port = system.membus.port
486242Sgblack@eecs.umich.edu
496242Sgblack@eecs.umich.edu
506242Sgblack@eecs.umich.edu# -----------------------
516242Sgblack@eecs.umich.edu# run simulation
526242Sgblack@eecs.umich.edu# -----------------------
536242Sgblack@eecs.umich.edu
546242Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
556242Sgblack@eecs.umich.eduroot.system.mem_mode = 'timing'
566242Sgblack@eecs.umich.edu