o3-timing-mp-ruby.py revision 8801:1a84c6a81299
16242Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 26242Sgblack@eecs.umich.edu# All rights reserved. 36242Sgblack@eecs.umich.edu# 46242Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 56242Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 66242Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 76242Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 86242Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 96242Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 106242Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 116242Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 126242Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 136242Sgblack@eecs.umich.edu# this software without specific prior written permission. 146242Sgblack@eecs.umich.edu# 156242Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166242Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176242Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186242Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196242Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206242Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216242Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226242Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236242Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246242Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256242Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266242Sgblack@eecs.umich.edu# 276242Sgblack@eecs.umich.edu# Authors: Ron Dreslinski 286242Sgblack@eecs.umich.edu 296242Sgblack@eecs.umich.eduimport m5 306242Sgblack@eecs.umich.edufrom m5.objects import * 316242Sgblack@eecs.umich.edum5.util.addToPath('../configs/common') 326242Sgblack@eecs.umich.edu 336242Sgblack@eecs.umich.edunb_cores = 4 346242Sgblack@eecs.umich.educpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 356242Sgblack@eecs.umich.edu 366242Sgblack@eecs.umich.eduimport ruby_config 376242Sgblack@eecs.umich.eduruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 386242Sgblack@eecs.umich.edu 396242Sgblack@eecs.umich.edu# system simulated 406242Sgblack@eecs.umich.edusystem = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 416242Sgblack@eecs.umich.edu 426242Sgblack@eecs.umich.edufor cpu in cpus: 436242Sgblack@eecs.umich.edu cpu.connectAllPorts(system.membus) 446242Sgblack@eecs.umich.edu cpu.clock = '2GHz' 456242Sgblack@eecs.umich.edu 466242Sgblack@eecs.umich.edu# connect memory to membus 476242Sgblack@eecs.umich.edusystem.physmem.port = system.membus.port 486242Sgblack@eecs.umich.edu 496242Sgblack@eecs.umich.edu 506242Sgblack@eecs.umich.edu# ----------------------- 516242Sgblack@eecs.umich.edu# run simulation 526242Sgblack@eecs.umich.edu# ----------------------- 536242Sgblack@eecs.umich.edu 546242Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 556242Sgblack@eecs.umich.eduroot.system.mem_mode = 'timing' 566242Sgblack@eecs.umich.edu