o3-timing-mp-ruby.py revision 8801:1a84c6a81299
12391SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 212218Snikos.nikoleris@arm.com# All rights reserved. 37733SN/A# 47733SN/A# Redistribution and use in source and binary forms, with or without 57733SN/A# modification, are permitted provided that the following conditions are 67733SN/A# met: redistributions of source code must retain the above copyright 77733SN/A# notice, this list of conditions and the following disclaimer; 87733SN/A# redistributions in binary form must reproduce the above copyright 97733SN/A# notice, this list of conditions and the following disclaimer in the 107733SN/A# documentation and/or other materials provided with the distribution; 117733SN/A# neither the name of the copyright holders nor the names of its 127733SN/A# contributors may be used to endorse or promote products derived from 137733SN/A# this software without specific prior written permission. 142391SN/A# 152391SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162391SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172391SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182391SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192391SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202391SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212391SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222391SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232391SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242391SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252391SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262391SN/A# 272391SN/A# Authors: Ron Dreslinski 282391SN/A 292391SN/Aimport m5 302391SN/Afrom m5.objects import * 312391SN/Am5.util.addToPath('../configs/common') 322391SN/A 332391SN/Anb_cores = 4 342391SN/Acpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 352391SN/A 362391SN/Aimport ruby_config 372391SN/Aruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 382391SN/A 392665SN/A# system simulated 402665SN/Asystem = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 412914SN/A 428931Sandreas.hansson@arm.comfor cpu in cpus: 432391SN/A cpu.connectAllPorts(system.membus) 442391SN/A cpu.clock = '2GHz' 4511793Sbrandon.potter@amd.com 4611793Sbrandon.potter@amd.com# connect memory to membus 4710466Sandreas.hansson@arm.comsystem.physmem.port = system.membus.port 4810466Sandreas.hansson@arm.com 4912218Snikos.nikoleris@arm.com 5010102Sali.saidi@arm.com# ----------------------- 5110102Sali.saidi@arm.com# run simulation 528232SN/A# ----------------------- 538232SN/A 543879SN/Aroot = Root(full_system = False, system = system) 559053Sdam.sunwoo@arm.comroot.system.mem_mode = 'timing' 562394SN/A