o3-timing-mp-ruby.py revision 9793
12207SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22207SN/A# All rights reserved. 32207SN/A# 42207SN/A# Redistribution and use in source and binary forms, with or without 52207SN/A# modification, are permitted provided that the following conditions are 62207SN/A# met: redistributions of source code must retain the above copyright 72207SN/A# notice, this list of conditions and the following disclaimer; 82207SN/A# redistributions in binary form must reproduce the above copyright 92207SN/A# notice, this list of conditions and the following disclaimer in the 102207SN/A# documentation and/or other materials provided with the distribution; 112207SN/A# neither the name of the copyright holders nor the names of its 122207SN/A# contributors may be used to endorse or promote products derived from 132207SN/A# this software without specific prior written permission. 142207SN/A# 152207SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162207SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172207SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182207SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192207SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202207SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212207SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222207SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232207SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242207SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252207SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262207SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduimport m5 302207SN/Afrom m5.objects import * 312207SN/Am5.util.addToPath('../configs/common') 322972Sgblack@eecs.umich.edum5.util.addToPath('../configs/topologies') 332207SN/A 348229Snate@binkert.orgnb_cores = 4 352454SN/Acpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 362454SN/A 372680Sktlim@umich.eduimport ruby_config 388232Snate@binkert.orgruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) 395759Shsul@eecs.umich.edu 407678Sgblack@eecs.umich.edu# system simulated 415759Shsul@eecs.umich.edusystem = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), 422474SN/A mem_mode = "timing", 432207SN/A clk_domain = SrcClockDomain(clock = '1GHz')) 442474SN/A 452474SN/A# Create a seperate clock domain for components that should run at 462474SN/A# CPUs frequency 475569Snate@binkert.orgsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 485569Snate@binkert.org 495154Sgblack@eecs.umich.edufor cpu in cpus: 502474SN/A # create the interrupt controller 512474SN/A cpu.createInterruptController() 5210318Sandreas.hansson@arm.com cpu.connectAllPorts(system.membus) 532474SN/A # All cpus are associated with cpu_clk_domain 542474SN/A cpu.clk_domain = system.cpu_clk_domain 552474SN/A 562474SN/A# connect memory to membus 572474SN/Asystem.physmem.port = system.membus.master 582474SN/A 592474SN/A# Connect the system port for loading of binaries etc 602474SN/Asystem.system_port = system.membus.slave 612474SN/A 622474SN/A# ----------------------- 632474SN/A# run simulation 642474SN/A# ----------------------- 652474SN/A 662474SN/Aroot = Root(full_system = False, system = system) 672474SN/Aroot.system.mem_mode = 'timing' 685759Shsul@eecs.umich.edu