o3-timing-checker.py revision 9790:ccc428657233 
1# Copyright (c) 2011 ARM Limited
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8# licensed hereunder.  You may use the software subject to the license
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24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Geoffrey Blake
37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41from Caches import *
42
43cpu = DerivO3CPU(cpu_id=0)
44cpu.createInterruptController()
45cpu.addCheckerCpu()
46cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
47                              L1Cache(size = '256kB'),
48                              L2Cache(size = '2MB'))
49# @todo Note that the L2 latency here is unmodified and 2 cycles,
50# should set hit latency and response latency to 20 cycles as for
51# other scripts
52cpu.clock = '2GHz'
53
54system = System(cpu = cpu,
55                physmem = DDR3_1600_x64(),
56                membus = CoherentBus(),
57                mem_mode = "timing")
58system.clock = '1GHz'
59system.system_port = system.membus.slave
60system.physmem.port = system.membus.master
61cpu.connectAllPorts(system.membus)
62
63root = Root(full_system = False, system = system)
64