o3-timing-checker.py revision 9311:227d19399b51
1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Geoffrey Blake 37 38import m5 39from m5.objects import * 40m5.util.addToPath('../configs/common') 41 42class MyCache(BaseCache): 43 assoc = 2 44 block_size = 64 45 hit_latency = 2 46 response_latency = 2 47 mshrs = 10 48 tgts_per_mshr = 5 49 50class MyL1Cache(MyCache): 51 is_top_level = True 52 tgts_per_mshr = 20 53 54cpu = DerivO3CPU(cpu_id=0) 55cpu.createInterruptController() 56cpu.addCheckerCpu() 57cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 58 MyL1Cache(size = '256kB'), 59 MyCache(size = '2MB')) 60# @todo Note that the L2 latency here is unmodified and 2 cycles, 61# should set hit latency and response latency to 20 cycles as for 62# other scripts 63cpu.clock = '2GHz' 64 65system = System(cpu = cpu, 66 physmem = SimpleDRAM(), 67 membus = CoherentBus()) 68system.system_port = system.membus.slave 69system.physmem.port = system.membus.master 70cpu.connectAllPorts(system.membus) 71 72root = Root(full_system = False, system = system) 73