o3-timing-checker.py revision 8889
18889Sgeoffrey.blake@arm.com# Copyright (c) 2011 ARM Limited 28889Sgeoffrey.blake@arm.com# All rights reserved 38889Sgeoffrey.blake@arm.com# 48889Sgeoffrey.blake@arm.com# The license below extends only to copyright in the software and shall 58889Sgeoffrey.blake@arm.com# not be construed as granting a license to any other intellectual 68889Sgeoffrey.blake@arm.com# property including but not limited to intellectual property relating 78889Sgeoffrey.blake@arm.com# to a hardware implementation of the functionality of the software 88889Sgeoffrey.blake@arm.com# licensed hereunder. You may use the software subject to the license 98889Sgeoffrey.blake@arm.com# terms below provided that you ensure that this notice is replicated 108889Sgeoffrey.blake@arm.com# unmodified and in its entirety in all distributions of the software, 118889Sgeoffrey.blake@arm.com# modified or unmodified, in source code or in binary form. 128889Sgeoffrey.blake@arm.com# 138889Sgeoffrey.blake@arm.com# Redistribution and use in source and binary forms, with or without 148889Sgeoffrey.blake@arm.com# modification, are permitted provided that the following conditions are 158889Sgeoffrey.blake@arm.com# met: redistributions of source code must retain the above copyright 168889Sgeoffrey.blake@arm.com# notice, this list of conditions and the following disclaimer; 178889Sgeoffrey.blake@arm.com# redistributions in binary form must reproduce the above copyright 188889Sgeoffrey.blake@arm.com# notice, this list of conditions and the following disclaimer in the 198889Sgeoffrey.blake@arm.com# documentation and/or other materials provided with the distribution; 208889Sgeoffrey.blake@arm.com# neither the name of the copyright holders nor the names of its 218889Sgeoffrey.blake@arm.com# contributors may be used to endorse or promote products derived from 228889Sgeoffrey.blake@arm.com# this software without specific prior written permission. 238889Sgeoffrey.blake@arm.com# 248889Sgeoffrey.blake@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 258889Sgeoffrey.blake@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 268889Sgeoffrey.blake@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 278889Sgeoffrey.blake@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 288889Sgeoffrey.blake@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 298889Sgeoffrey.blake@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 308889Sgeoffrey.blake@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 318889Sgeoffrey.blake@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 328889Sgeoffrey.blake@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 338889Sgeoffrey.blake@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 348889Sgeoffrey.blake@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 358889Sgeoffrey.blake@arm.com# 368889Sgeoffrey.blake@arm.com# Authors: Geoffrey Blake 378889Sgeoffrey.blake@arm.com 388889Sgeoffrey.blake@arm.comimport m5 398889Sgeoffrey.blake@arm.comfrom m5.objects import * 408889Sgeoffrey.blake@arm.comm5.util.addToPath('../configs/common') 418889Sgeoffrey.blake@arm.com 428889Sgeoffrey.blake@arm.comclass MyCache(BaseCache): 438889Sgeoffrey.blake@arm.com assoc = 2 448889Sgeoffrey.blake@arm.com block_size = 64 458889Sgeoffrey.blake@arm.com latency = '1ns' 468889Sgeoffrey.blake@arm.com mshrs = 10 478889Sgeoffrey.blake@arm.com tgts_per_mshr = 5 488889Sgeoffrey.blake@arm.com 498889Sgeoffrey.blake@arm.comclass MyL1Cache(MyCache): 508889Sgeoffrey.blake@arm.com is_top_level = True 518889Sgeoffrey.blake@arm.com tgts_per_mshr = 20 528889Sgeoffrey.blake@arm.com 538889Sgeoffrey.blake@arm.comcpu = DerivO3CPU(cpu_id=0) 548889Sgeoffrey.blake@arm.comcpu.createInterruptController() 558889Sgeoffrey.blake@arm.comcpu.addCheckerCpu() 568889Sgeoffrey.blake@arm.comcpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 578889Sgeoffrey.blake@arm.com MyL1Cache(size = '256kB'), 588889Sgeoffrey.blake@arm.com MyCache(size = '2MB')) 598889Sgeoffrey.blake@arm.comcpu.clock = '2GHz' 608889Sgeoffrey.blake@arm.com 618889Sgeoffrey.blake@arm.comsystem = System(cpu = cpu, 628889Sgeoffrey.blake@arm.com physmem = PhysicalMemory(), 638889Sgeoffrey.blake@arm.com membus = Bus()) 648889Sgeoffrey.blake@arm.comsystem.system_port = system.membus.slave 658889Sgeoffrey.blake@arm.comsystem.physmem.port = system.membus.master 668889Sgeoffrey.blake@arm.comcpu.connectAllPorts(system.membus) 678889Sgeoffrey.blake@arm.com 688889Sgeoffrey.blake@arm.comroot = Root(full_system = False, system = system) 69