memtest.py revision 9790:ccc428657233
17019SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27019SBrad.Beckmann@amd.com# All rights reserved. 37019SBrad.Beckmann@amd.com# 47019SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 57019SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 67019SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 77019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 87019SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 97019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 107019SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 117019SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 127019SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 137019SBrad.Beckmann@amd.com# this software without specific prior written permission. 147019SBrad.Beckmann@amd.com# 157019SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167019SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177019SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187019SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197019SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207019SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217019SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227019SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237019SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247019SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257019SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267019SBrad.Beckmann@amd.com# 277019SBrad.Beckmann@amd.com# Authors: Ron Dreslinski 287019SBrad.Beckmann@amd.com 297019SBrad.Beckmann@amd.comimport m5 306876Ssteve.reinhardt@amd.comfrom m5.objects import * 316882SBrad.Beckmann@amd.comm5.util.addToPath('../configs/common') 326876Ssteve.reinhardt@amd.comfrom Caches import * 336876Ssteve.reinhardt@amd.com 346876Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method 3511308Santhony.gutierrez@amd.comnb_cores = 8 3611308Santhony.gutierrez@amd.comcpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 3711308Santhony.gutierrez@amd.com 3811308Santhony.gutierrez@amd.com# system simulated 3910090Snilay@cs.wisc.edusystem = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 4011308Santhony.gutierrez@amd.com funcbus = NoncoherentBus(), 4111308Santhony.gutierrez@amd.com physmem = SimpleMemory(), 4211308Santhony.gutierrez@amd.com membus = CoherentBus(width=16)) 4311308Santhony.gutierrez@amd.comsystem.clock = '1GHz' 4411308Santhony.gutierrez@amd.com 4511308Santhony.gutierrez@amd.com# l2cache & bus 4610090Snilay@cs.wisc.edusystem.toL2Bus = CoherentBus(clock="2GHz", width=16) 4711308Santhony.gutierrez@amd.comsystem.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 4811308Santhony.gutierrez@amd.comsystem.l2c.cpu_side = system.toL2Bus.master 4911308Santhony.gutierrez@amd.com 5011308Santhony.gutierrez@amd.com# connect l2c to membus 5111308Santhony.gutierrez@amd.comsystem.l2c.mem_side = system.membus.slave 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.com# add L1 caches 548932SBrad.Beckmann@amd.comfor cpu in cpus: 558706Sandreas.hansson@arm.com cpu.l1c = L1Cache(size = '32kB', assoc = 4) 5611308Santhony.gutierrez@amd.com cpu.l1c.cpu_side = cpu.test 5711308Santhony.gutierrez@amd.com cpu.l1c.mem_side = system.toL2Bus.slave 5810919Sbrandon.potter@amd.com system.funcbus.slave = cpu.functional 596876Ssteve.reinhardt@amd.com 6011308Santhony.gutierrez@amd.comsystem.system_port = system.membus.slave 6111308Santhony.gutierrez@amd.com 6211308Santhony.gutierrez@amd.com# connect reference memory to funcbus 6310090Snilay@cs.wisc.edusystem.funcmem.port = system.funcbus.master 6411308Santhony.gutierrez@amd.com 6511308Santhony.gutierrez@amd.com# connect memory to membus 6611308Santhony.gutierrez@amd.comsystem.physmem.port = system.membus.master 6711308Santhony.gutierrez@amd.com 6811308Santhony.gutierrez@amd.com 6911308Santhony.gutierrez@amd.com# ----------------------- 7011308Santhony.gutierrez@amd.com# run simulation 7111308Santhony.gutierrez@amd.com# ----------------------- 7211308Santhony.gutierrez@amd.com 7311308Santhony.gutierrez@amd.comroot = Root( full_system = False, system = system ) 7411308Santhony.gutierrez@amd.comroot.system.mem_mode = 'timing' 7511308Santhony.gutierrez@amd.com#root.trace.flags="Cache CachePort MemoryAccess" 7611660Stushar@ece.gatech.edu#root.trace.cycle=1 7711308Santhony.gutierrez@amd.com 7811308Santhony.gutierrez@amd.com