memtest.py revision 9788:5558ee8dd7d9
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), 42 membus = CoherentBus(width=16)) 43 44# l2cache & bus 45system.toL2Bus = CoherentBus(clock="2GHz", width=16) 46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 47system.l2c.cpu_side = system.toL2Bus.master 48 49# connect l2c to membus 50system.l2c.mem_side = system.membus.slave 51 52# add L1 caches 53for cpu in cpus: 54 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 55 cpu.l1c.cpu_side = cpu.test 56 cpu.l1c.mem_side = system.toL2Bus.slave 57 system.funcbus.slave = cpu.functional 58 59system.system_port = system.membus.slave 60 61# connect reference memory to funcbus 62system.funcmem.port = system.funcbus.master 63 64# connect memory to membus 65system.physmem.port = system.membus.master 66 67 68# ----------------------- 69# run simulation 70# ----------------------- 71 72root = Root( full_system = False, system = system ) 73root.system.mem_mode = 'timing' 74#root.trace.flags="Cache CachePort MemoryAccess" 75#root.trace.cycle=1 76 77