memtest.py revision 8839:eeb293859255
112SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210037SARM gem5 Developers# All rights reserved. 310037SARM gem5 Developers# 410037SARM gem5 Developers# Redistribution and use in source and binary forms, with or without 510037SARM gem5 Developers# modification, are permitted provided that the following conditions are 610037SARM gem5 Developers# met: redistributions of source code must retain the above copyright 710037SARM gem5 Developers# notice, this list of conditions and the following disclaimer; 810037SARM gem5 Developers# redistributions in binary form must reproduce the above copyright 910037SARM gem5 Developers# notice, this list of conditions and the following disclaimer in the 1010037SARM gem5 Developers# documentation and/or other materials provided with the distribution; 1110037SARM gem5 Developers# neither the name of the copyright holders nor the names of its 1210037SARM gem5 Developers# contributors may be used to endorse or promote products derived from 1310037SARM gem5 Developers# this software without specific prior written permission. 141762SN/A# 1512SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1612SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1712SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1812SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1912SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2012SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2112SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2212SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2312SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2412SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2512SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2612SN/A# 2712SN/A# Authors: Ron Dreslinski 2812SN/A 2912SN/Aimport m5 3012SN/Afrom m5.objects import * 3112SN/A 3212SN/A# -------------------- 3312SN/A# Base L1 Cache 3412SN/A# ==================== 3512SN/A 3612SN/Aclass L1(BaseCache): 3712SN/A latency = '1ns' 3812SN/A block_size = 64 392665Ssaidi@eecs.umich.edu mshrs = 12 402665Ssaidi@eecs.umich.edu tgts_per_mshr = 8 412665Ssaidi@eecs.umich.edu is_top_level = True 4212SN/A 4312SN/A# ---------------------- 4411389Sbrandon.potter@amd.com# Base L2 Cache 4511389Sbrandon.potter@amd.com# ---------------------- 4611389Sbrandon.potter@amd.com 4711389Sbrandon.potter@amd.comclass L2(BaseCache): 4811389Sbrandon.potter@amd.com block_size = 64 4911389Sbrandon.potter@amd.com latency = '10ns' 5011389Sbrandon.potter@amd.com mshrs = 92 5111389Sbrandon.potter@amd.com tgts_per_mshr = 16 525616Snate@binkert.org write_buffers = 8 5312SN/A 5412SN/A#MAX CORES IS 8 with the fals sharing method 5511389Sbrandon.potter@amd.comnb_cores = 8 564484Sbinkertn@umich.educpus = [ MemTest() for i in xrange(nb_cores) ] 572439SN/A 587676Snate@binkert.org# system simulated 598232Snate@binkert.orgsystem = System(cpu = cpus, funcmem = PhysicalMemory(), 6011389Sbrandon.potter@amd.com physmem = PhysicalMemory(), 612423SN/A membus = Bus(clock="500GHz", width=16)) 622423SN/A 6312SN/A# l2cache & bus 6411391Sbrandon.potter@amd.comsystem.toL2Bus = Bus(clock="500GHz", width=16) 6511389Sbrandon.potter@amd.comsystem.l2c = L2(size='64kB', assoc=8) 6612SN/Asystem.l2c.cpu_side = system.toL2Bus.master 67468SN/A 681708SN/A# connect l2c to membus 691708SN/Asystem.l2c.mem_side = system.membus.slave 70443SN/A 71468SN/A# add L1 caches 7211391Sbrandon.potter@amd.comfor cpu in cpus: 7311391Sbrandon.potter@amd.com cpu.l1c = L1(size = '32kB', assoc = 4) 7411391Sbrandon.potter@amd.com cpu.l1c.cpu_side = cpu.test 75443SN/A cpu.l1c.mem_side = system.toL2Bus.slave 7611391Sbrandon.potter@amd.com system.funcmem.port = cpu.functional 7710037SARM gem5 Developers 78443SN/Asystem.system_port = system.membus.slave 79443SN/A 80443SN/A# connect memory to membus 8111391Sbrandon.potter@amd.comsystem.physmem.port = system.membus.master 8211391Sbrandon.potter@amd.com 8311391Sbrandon.potter@amd.com 8411391Sbrandon.potter@amd.com# ----------------------- 8511391Sbrandon.potter@amd.com# run simulation 8611391Sbrandon.potter@amd.com# ----------------------- 8711391Sbrandon.potter@amd.com 8811391Sbrandon.potter@amd.comroot = Root( full_system = False, system = system ) 8911391Sbrandon.potter@amd.comroot.system.mem_mode = 'timing' 9011391Sbrandon.potter@amd.com#root.trace.flags="Cache CachePort MemoryAccess" 9111391Sbrandon.potter@amd.com#root.trace.cycle=1 9211391Sbrandon.potter@amd.com 9311391Sbrandon.potter@amd.com