memtest.py revision 8706:b1838faf3bcc 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37    latency = '1ns'
38    block_size = 64
39    mshrs = 12
40    tgts_per_mshr = 8
41    is_top_level = True
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48    block_size = 64
49    latency = '10ns'
50    mshrs = 92
51    tgts_per_mshr = 16
52    write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
56cpus = [ MemTest() for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60                physmem = PhysicalMemory(),
61                membus = Bus(clock="500GHz", width=16))
62
63# l2cache & bus
64system.toL2Bus = Bus(clock="500GHz", width=16)
65system.l2c = L2(size='64kB', assoc=8)
66system.l2c.cpu_side = system.toL2Bus.port
67system.l2c.num_cpus = nb_cores
68
69# connect l2c to membus
70system.l2c.mem_side = system.membus.port
71
72# add L1 caches
73for cpu in cpus:
74    cpu.l1c = L1(size = '32kB', assoc = 4)
75    cpu.l1c.cpu_side = cpu.test
76    cpu.l1c.mem_side = system.toL2Bus.port
77    system.funcmem.port = cpu.functional
78
79system.system_port = system.membus.port
80
81# connect memory to membus
82system.physmem.port = system.membus.port
83
84
85# -----------------------
86# run simulation
87# -----------------------
88
89root = Root( system = system )
90root.system.mem_mode = 'timing'
91#root.trace.flags="Cache CachePort MemoryAccess"
92#root.trace.cycle=1
93
94