memtest.py revision 3257:269df2f3bb2b 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37    latency = 1
38    block_size = 64
39    mshrs = 12
40    tgts_per_mshr = 8
41    protocol = CoherenceProtocol(protocol='moesi')
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48    block_size = 64
49    latency = 10
50    mshrs = 92
51    tgts_per_mshr = 16
52    write_buffers = 8
53
54#MAX CORES IS 8 with the fals sharing method
55nb_cores = 8
56cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
57
58# system simulated
59system = System(cpu = cpus, funcmem = PhysicalMemory(),
60                physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
61
62# l2cache & bus
63system.toL2Bus = Bus(clock="500GHz", width=16)
64system.l2c = L2(size='64kB', assoc=8)
65system.l2c.cpu_side = system.toL2Bus.port
66
67# connect l2c to membus
68system.l2c.mem_side = system.membus.port
69
70which_port = 0
71# add L1 caches
72for cpu in cpus:
73    cpu.l1c = L1(size = '32kB', assoc = 4)
74    cpu.l1c.cpu_side = cpu.test
75    cpu.l1c.mem_side = system.toL2Bus.port
76    if  which_port == 0:
77         system.funcmem.port = cpu.functional
78         which_port = 1
79    else:
80         system.funcmem.functional = cpu.functional
81
82
83# connect memory to membus
84system.physmem.port = system.membus.port
85
86
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root( system = system )
92root.system.mem_mode = 'timing'
93#root.trace.flags="Cache CachePort Bus"
94#root.trace.cycle=3810800
95
96