memtest.py revision 9827 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest() for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
40                funcbus = NoncoherentBus(),
41                physmem = SimpleMemory(),
42                membus = CoherentBus(width=16))
43# Dummy voltage domain for all our clock domains
44system.voltage_domain = VoltageDomain()
45system.clk_domain = SrcClockDomain(clock = '1GHz',
46                                   voltage_domain = system.voltage_domain)
47
48# Create a seperate clock domain for components that should run at
49# CPUs frequency
50system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
51                                       voltage_domain = system.voltage_domain)
52
53system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
55system.l2c.cpu_side = system.toL2Bus.master
56
57# connect l2c to membus
58system.l2c.mem_side = system.membus.slave
59
60# add L1 caches
61for cpu in cpus:
62    # All cpus are associated with cpu_clk_domain
63    cpu.clk_domain = system.cpu_clk_domain
64    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
65    cpu.l1c.cpu_side = cpu.test
66    cpu.l1c.mem_side = system.toL2Bus.slave
67    system.funcbus.slave = cpu.functional
68
69system.system_port = system.membus.slave
70
71# connect reference memory to funcbus
72system.funcmem.port = system.funcbus.master
73
74# connect memory to membus
75system.physmem.port = system.membus.master
76
77
78# -----------------------
79# run simulation
80# -----------------------
81
82root = Root( full_system = False, system = system )
83root.system.mem_mode = 'timing'
84#root.trace.flags="Cache CachePort MemoryAccess"
85#root.trace.cycle=1
86
87