memtest.py revision 9321
14019Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23187Srdreslin@umich.edu# All rights reserved. 33187Srdreslin@umich.edu# 43187Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 53187Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 63187Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 73187Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 83187Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 93187Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 103187Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 113187Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 123187Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 133187Srdreslin@umich.edu# this software without specific prior written permission. 143187Srdreslin@umich.edu# 153187Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163187Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173187Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183187Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193187Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203187Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213187Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223187Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233187Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243187Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253187Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263187Srdreslin@umich.edu# 273187Srdreslin@umich.edu# Authors: Ron Dreslinski 283187Srdreslin@umich.edu 293187Srdreslin@umich.eduimport m5 303187Srdreslin@umich.edufrom m5.objects import * 319321Sandreas.hansson@arm.comm5.util.addToPath('../configs/common') 329321Sandreas.hansson@arm.comfrom Caches import * 333187Srdreslin@umich.edu 343196Srdreslin@umich.edu#MAX CORES IS 8 with the fals sharing method 353196Srdreslin@umich.edunb_cores = 8 369286Sandreas.hansson@arm.comcpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 373187Srdreslin@umich.edu 383187Srdreslin@umich.edu# system simulated 398931Sandreas.hansson@arm.comsystem = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 409120Sandreas.hansson@arm.com funcbus = NoncoherentBus(), 418931Sandreas.hansson@arm.com physmem = SimpleMemory(), 429286Sandreas.hansson@arm.com membus = CoherentBus(clock="1GHz", width=16)) 433187Srdreslin@umich.edu 443187Srdreslin@umich.edu# l2cache & bus 459286Sandreas.hansson@arm.comsystem.toL2Bus = CoherentBus(clock="2GHz", width=16) 469321Sandreas.hansson@arm.comsystem.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 478839Sandreas.hansson@arm.comsystem.l2c.cpu_side = system.toL2Bus.master 483187Srdreslin@umich.edu 493187Srdreslin@umich.edu# connect l2c to membus 508839Sandreas.hansson@arm.comsystem.l2c.mem_side = system.membus.slave 513187Srdreslin@umich.edu 523187Srdreslin@umich.edu# add L1 caches 533187Srdreslin@umich.edufor cpu in cpus: 549321Sandreas.hansson@arm.com cpu.l1c = L1Cache(size = '32kB', assoc = 4) 553187Srdreslin@umich.edu cpu.l1c.cpu_side = cpu.test 568839Sandreas.hansson@arm.com cpu.l1c.mem_side = system.toL2Bus.slave 579120Sandreas.hansson@arm.com system.funcbus.slave = cpu.functional 583187Srdreslin@umich.edu 598839Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 608706Sandreas.hansson@arm.com 619120Sandreas.hansson@arm.com# connect reference memory to funcbus 629120Sandreas.hansson@arm.comsystem.funcmem.port = system.funcbus.master 639120Sandreas.hansson@arm.com 643187Srdreslin@umich.edu# connect memory to membus 658839Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master 663187Srdreslin@umich.edu 673187Srdreslin@umich.edu 683187Srdreslin@umich.edu# ----------------------- 693187Srdreslin@umich.edu# run simulation 703187Srdreslin@umich.edu# ----------------------- 713187Srdreslin@umich.edu 728801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 733187Srdreslin@umich.eduroot.system.mem_mode = 'timing' 743341Srdreslin@umich.edu#root.trace.flags="Cache CachePort MemoryAccess" 753341Srdreslin@umich.edu#root.trace.cycle=1 763257Srdreslin@umich.edu 77