memtest.py revision 9120
14019Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23187Srdreslin@umich.edu# All rights reserved. 33187Srdreslin@umich.edu# 43187Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 53187Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 63187Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 73187Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 83187Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 93187Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 103187Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 113187Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 123187Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 133187Srdreslin@umich.edu# this software without specific prior written permission. 143187Srdreslin@umich.edu# 153187Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163187Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173187Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183187Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193187Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203187Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213187Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223187Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233187Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243187Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253187Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263187Srdreslin@umich.edu# 273187Srdreslin@umich.edu# Authors: Ron Dreslinski 283187Srdreslin@umich.edu 293187Srdreslin@umich.eduimport m5 303187Srdreslin@umich.edufrom m5.objects import * 313187Srdreslin@umich.edu 323187Srdreslin@umich.edu# -------------------- 333187Srdreslin@umich.edu# Base L1 Cache 343187Srdreslin@umich.edu# ==================== 353187Srdreslin@umich.edu 363187Srdreslin@umich.educlass L1(BaseCache): 374444Ssaidi@eecs.umich.edu latency = '1ns' 383187Srdreslin@umich.edu block_size = 64 393208Srdreslin@umich.edu mshrs = 12 403187Srdreslin@umich.edu tgts_per_mshr = 8 418134SAli.Saidi@ARM.com is_top_level = True 423187Srdreslin@umich.edu 433187Srdreslin@umich.edu# ---------------------- 443187Srdreslin@umich.edu# Base L2 Cache 453187Srdreslin@umich.edu# ---------------------- 463187Srdreslin@umich.edu 473187Srdreslin@umich.educlass L2(BaseCache): 483187Srdreslin@umich.edu block_size = 64 494444Ssaidi@eecs.umich.edu latency = '10ns' 503187Srdreslin@umich.edu mshrs = 92 513187Srdreslin@umich.edu tgts_per_mshr = 16 523187Srdreslin@umich.edu write_buffers = 8 533187Srdreslin@umich.edu 543196Srdreslin@umich.edu#MAX CORES IS 8 with the fals sharing method 553196Srdreslin@umich.edunb_cores = 8 564019Sstever@eecs.umich.educpus = [ MemTest() for i in xrange(nb_cores) ] 573187Srdreslin@umich.edu 583187Srdreslin@umich.edu# system simulated 598931Sandreas.hansson@arm.comsystem = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 609120Sandreas.hansson@arm.com funcbus = NoncoherentBus(), 618931Sandreas.hansson@arm.com physmem = SimpleMemory(), 629036Sandreas.hansson@arm.com membus = CoherentBus(clock="500GHz", width=16)) 633187Srdreslin@umich.edu 643187Srdreslin@umich.edu# l2cache & bus 659036Sandreas.hansson@arm.comsystem.toL2Bus = CoherentBus(clock="500GHz", width=16) 663208Srdreslin@umich.edusystem.l2c = L2(size='64kB', assoc=8) 678839Sandreas.hansson@arm.comsystem.l2c.cpu_side = system.toL2Bus.master 683187Srdreslin@umich.edu 693187Srdreslin@umich.edu# connect l2c to membus 708839Sandreas.hansson@arm.comsystem.l2c.mem_side = system.membus.slave 713187Srdreslin@umich.edu 723187Srdreslin@umich.edu# add L1 caches 733187Srdreslin@umich.edufor cpu in cpus: 743187Srdreslin@umich.edu cpu.l1c = L1(size = '32kB', assoc = 4) 753187Srdreslin@umich.edu cpu.l1c.cpu_side = cpu.test 768839Sandreas.hansson@arm.com cpu.l1c.mem_side = system.toL2Bus.slave 779120Sandreas.hansson@arm.com system.funcbus.slave = cpu.functional 783187Srdreslin@umich.edu 798839Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 808706Sandreas.hansson@arm.com 819120Sandreas.hansson@arm.com# connect reference memory to funcbus 829120Sandreas.hansson@arm.comsystem.funcmem.port = system.funcbus.master 839120Sandreas.hansson@arm.com 843187Srdreslin@umich.edu# connect memory to membus 858839Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master 863187Srdreslin@umich.edu 873187Srdreslin@umich.edu 883187Srdreslin@umich.edu# ----------------------- 893187Srdreslin@umich.edu# run simulation 903187Srdreslin@umich.edu# ----------------------- 913187Srdreslin@umich.edu 928801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 933187Srdreslin@umich.eduroot.system.mem_mode = 'timing' 943341Srdreslin@umich.edu#root.trace.flags="Cache CachePort MemoryAccess" 953341Srdreslin@umich.edu#root.trace.cycle=1 963257Srdreslin@umich.edu 97