memtest-ruby.py revision 8436
12315SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
22332SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc.
32315SN/A# All rights reserved.
42315SN/A#
52315SN/A# Redistribution and use in source and binary forms, with or without
62315SN/A# modification, are permitted provided that the following conditions are
72315SN/A# met: redistributions of source code must retain the above copyright
82315SN/A# notice, this list of conditions and the following disclaimer;
92315SN/A# redistributions in binary form must reproduce the above copyright
102315SN/A# notice, this list of conditions and the following disclaimer in the
112315SN/A# documentation and/or other materials provided with the distribution;
122315SN/A# neither the name of the copyright holders nor the names of its
132315SN/A# contributors may be used to endorse or promote products derived from
142315SN/A# this software without specific prior written permission.
152315SN/A#
162315SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172315SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182315SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192315SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202315SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212315SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222315SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232315SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242315SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252315SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262315SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272689SN/A#
282689SN/A# Authors: Ron Dreslinski
292315SN/A
302315SN/Aimport m5
312315SN/Afrom m5.objects import *
322315SN/Afrom m5.defines import buildEnv
332315SN/Afrom m5.util import addToPath
342315SN/Aimport os, optparse, sys
352315SN/A
362315SN/Aif buildEnv['FULL_SYSTEM']:
372683SN/A    panic("This script requires system-emulation mode (*_SE).")
382680SN/A
392315SN/A# Get paths we might need
402722SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__))
412315SN/Aconfig_root = os.path.dirname(config_path)
422315SN/Am5_root = os.path.dirname(config_root)
432315SN/AaddToPath(config_root+'/configs/common')
442315SN/AaddToPath(config_root+'/configs/ruby')
452315SN/A
462315SN/Aimport Ruby
472315SN/A
482315SN/Aparser = optparse.OptionParser()
492315SN/A
502315SN/A#
512315SN/A# Add the ruby specific and protocol specific options
522315SN/A#
532315SN/ARuby.define_options(parser)
542315SN/A
552732SN/Aexecfile(os.path.join(config_root, "configs/common", "Options.py"))
562315SN/A
572315SN/A(options, args) = parser.parse_args()
582315SN/A
592332SN/A#
602332SN/A# Set the default cache size and associativity to be very small to encourage
612332SN/A# races between requests and writebacks.
622332SN/A#
632332SN/Aoptions.l1d_size="256B"
642315SN/Aoptions.l1i_size="256B"
652315SN/Aoptions.l2_size="512B"
662315SN/Aoptions.l3_size="1kB"
672315SN/Aoptions.l1d_assoc=2
682315SN/Aoptions.l1i_assoc=2
692315SN/Aoptions.l2_assoc=2
702315SN/Aoptions.l3_assoc=2
712315SN/A
722315SN/A#MAX CORES IS 8 with the fals sharing method
732315SN/Anb_cores = 8
742315SN/A
752315SN/A# ruby does not support atomic, functional, or uncacheable accesses
762315SN/Acpus = [ MemTest(atomic=False, percent_functional=50,
772315SN/A                 percent_uncacheable=0, suppress_func_warnings=True) \
782315SN/A         for i in xrange(nb_cores) ]
792315SN/A
802315SN/A# overwrite options.num_cpus with the nb_cores value
812315SN/Aoptions.num_cpus = nb_cores
822315SN/A
832315SN/A# system simulated
842315SN/Asystem = System(cpu = cpus,
852315SN/A                funcmem = PhysicalMemory(),
862315SN/A                physmem = PhysicalMemory())
872315SN/A
882315SN/ARuby.create_system(options, system)
892315SN/A
902315SN/Aassert(len(cpus) == len(system.ruby._cpu_ruby_ports))
912315SN/A
922315SN/Afor (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
932315SN/A     #
942315SN/A     # Tie the cpu test and functional ports to the ruby cpu ports and
952315SN/A     # physmem, respectively
962315SN/A     #
972332SN/A     cpus[i].test = ruby_port.port
982332SN/A     cpus[i].functional = system.funcmem.port
992332SN/A
1002315SN/A     #
1012315SN/A     # Since the memtester is incredibly bursty, increase the deadlock
1022315SN/A     # threshold to 1 million cycles
1032315SN/A     #
1042315SN/A     ruby_port.deadlock_threshold = 1000000
1052679SN/A
1062315SN/A     #
1072315SN/A     # Ruby doesn't need the backing image of memory when running with
1082315SN/A     # the tester.
1092315SN/A     #
1102315SN/A     ruby_port.access_phys_mem = False
1112683SN/A
1122315SN/A# -----------------------
1132683SN/A# run simulation
1142315SN/A# -----------------------
1152315SN/A
1162332SN/Aroot = Root(system = system)
1172332SN/Aroot.system.mem_mode = 'timing'
1182332SN/A
1192315SN/A# Not much point in this being higher than the L1 latency
1202315SN/Am5.ticks.setGlobalFrequency('1ns')
1212683SN/A