memtest-filter.py revision 9321 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
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27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
40                funcbus = NoncoherentBus(),
41                physmem = SimpleMemory(),
42                membus = CoherentBus(clock="1GHz", width=16))
43
44# l2cache & bus
45system.toL2Bus = CoherentBus(clock="2GHz", width=16)
46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
47system.l2c.cpu_side = system.toL2Bus.master
48
49# connect l2c to membus
50system.l2c.mem_side = system.membus.slave
51
52# add L1 caches
53for cpu in cpus:
54    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
55    cpu.l1c.cpu_side = cpu.test
56    cpu.l1c.mem_side = system.toL2Bus.slave
57    system.funcbus.slave = cpu.functional
58
59system.system_port = system.membus.slave
60
61# connect reference memory to funcbus
62system.funcmem.port = system.funcbus.master
63
64# connect memory to membus
65system.physmem.port = system.membus.master
66
67
68# -----------------------
69# run simulation
70# -----------------------
71
72root = Root( full_system = False, system = system )
73root.system.mem_mode = 'timing'
74#root.trace.flags="Cache CachePort MemoryAccess"
75#root.trace.cycle=1
76
77