memtest-filter.py revision 9321
11689SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21689SN/A# All rights reserved. 31689SN/A# 41689SN/A# Redistribution and use in source and binary forms, with or without 51689SN/A# modification, are permitted provided that the following conditions are 61689SN/A# met: redistributions of source code must retain the above copyright 71689SN/A# notice, this list of conditions and the following disclaimer; 81689SN/A# redistributions in binary form must reproduce the above copyright 91689SN/A# notice, this list of conditions and the following disclaimer in the 101689SN/A# documentation and/or other materials provided with the distribution; 111689SN/A# neither the name of the copyright holders nor the names of its 121689SN/A# contributors may be used to endorse or promote products derived from 131689SN/A# this software without specific prior written permission. 141689SN/A# 151689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261689SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 291689SN/Aimport m5 301060SN/Afrom m5.objects import * 318229Snate@binkert.orgm5.util.addToPath('../configs/common') 322817Sksewell@umich.edufrom Caches import * 331060SN/A 342818Sksewell@umich.edu#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] 37 38# system simulated 39system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), 40 funcbus = NoncoherentBus(), 41 physmem = SimpleMemory(), 42 membus = CoherentBus(clock="1GHz", width=16)) 43 44# l2cache & bus 45system.toL2Bus = CoherentBus(clock="2GHz", width=16) 46system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) 47system.l2c.cpu_side = system.toL2Bus.master 48 49# connect l2c to membus 50system.l2c.mem_side = system.membus.slave 51 52# add L1 caches 53for cpu in cpus: 54 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 55 cpu.l1c.cpu_side = cpu.test 56 cpu.l1c.mem_side = system.toL2Bus.slave 57 system.funcbus.slave = cpu.functional 58 59system.system_port = system.membus.slave 60 61# connect reference memory to funcbus 62system.funcmem.port = system.funcbus.master 63 64# connect memory to membus 65system.physmem.port = system.membus.master 66 67 68# ----------------------- 69# run simulation 70# ----------------------- 71 72root = Root( full_system = False, system = system ) 73root.system.mem_mode = 'timing' 74#root.trace.flags="Cache CachePort MemoryAccess" 75#root.trace.cycle=1 76 77