arm_generic.py revision 12070:d89ac2ebc159
112337Sjason@lowepower.com# Copyright (c) 2012, 2017 ARM Limited 212337Sjason@lowepower.com# All rights reserved. 312337Sjason@lowepower.com# 412337Sjason@lowepower.com# The license below extends only to copyright in the software and shall 512337Sjason@lowepower.com# not be construed as granting a license to any other intellectual 612337Sjason@lowepower.com# property including but not limited to intellectual property relating 712337Sjason@lowepower.com# to a hardware implementation of the functionality of the software 812337Sjason@lowepower.com# licensed hereunder. You may use the software subject to the license 912337Sjason@lowepower.com# terms below provided that you ensure that this notice is replicated 1012337Sjason@lowepower.com# unmodified and in its entirety in all distributions of the software, 1112337Sjason@lowepower.com# modified or unmodified, in source code or in binary form. 1212337Sjason@lowepower.com# 1312337Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 1412337Sjason@lowepower.com# modification, are permitted provided that the following conditions are 1512337Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 1612337Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 1712337Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 1812337Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1912337Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 2012337Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 2112337Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 2212337Sjason@lowepower.com# this software without specific prior written permission. 2312337Sjason@lowepower.com# 2412337Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2512337Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2612337Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2712337Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2812337Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2912337Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3012337Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3112337Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3212337Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3312337Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3412337Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3512337Sjason@lowepower.com# 3612337Sjason@lowepower.com# Authors: Andreas Sandberg 3712337Sjason@lowepower.com 3812337Sjason@lowepower.comfrom abc import ABCMeta, abstractmethod 3912337Sjason@lowepower.comimport m5 4012337Sjason@lowepower.comfrom m5.objects import * 4112337Sjason@lowepower.comfrom m5.proxy import * 4212337Sjason@lowepower.comm5.util.addToPath('../configs/') 4312337Sjason@lowepower.comfrom common import FSConfig 4412337Sjason@lowepower.comfrom common.Caches import * 4512337Sjason@lowepower.comfrom base_config import * 4612337Sjason@lowepower.comfrom common.O3_ARM_v7a import * 4712337Sjason@lowepower.comfrom common.Benchmarks import SysConfig 4812337Sjason@lowepower.com 4912337Sjason@lowepower.comclass ArmSESystemUniprocessor(BaseSESystemUniprocessor): 5012337Sjason@lowepower.com """Syscall-emulation builder for ARM uniprocessor systems. 5112337Sjason@lowepower.com 5212337Sjason@lowepower.com A small tweak of the syscall-emulation builder to use more 5312337Sjason@lowepower.com representative cache configurations. 5412337Sjason@lowepower.com """ 5512337Sjason@lowepower.com 5612337Sjason@lowepower.com def __init__(self, **kwargs): 5712337Sjason@lowepower.com BaseSESystem.__init__(self, **kwargs) 5812337Sjason@lowepower.com 5912337Sjason@lowepower.com def create_caches_private(self, cpu): 6012337Sjason@lowepower.com # The atomic SE configurations do not use caches 6112337Sjason@lowepower.com if self.mem_mode == "timing": 6212337Sjason@lowepower.com # Use the more representative cache configuration 6312337Sjason@lowepower.com cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 6412337Sjason@lowepower.com O3_ARM_v7a_DCache(), 6512337Sjason@lowepower.com O3_ARM_v7aL2()) 6612337Sjason@lowepower.com 6712337Sjason@lowepower.comclass LinuxArmSystemBuilder(object): 6812337Sjason@lowepower.com """Mix-in that implements create_system. 6912337Sjason@lowepower.com 7012337Sjason@lowepower.com This mix-in is intended as a convenient way of adding an 7112337Sjason@lowepower.com ARM-specific create_system method to a class deriving from one of 7212337Sjason@lowepower.com the generic base systems. 7312337Sjason@lowepower.com """ 7412337Sjason@lowepower.com def __init__(self, machine_type, **kwargs): 7512337Sjason@lowepower.com """ 7612337Sjason@lowepower.com Arguments: 7712337Sjason@lowepower.com machine_type -- String describing the platform to simulate 7812337Sjason@lowepower.com num_cpus -- integer number of CPUs in the system 7912337Sjason@lowepower.com use_ruby -- True if ruby is used instead of the classic memory system 8012337Sjason@lowepower.com """ 8112337Sjason@lowepower.com self.machine_type = machine_type 8212337Sjason@lowepower.com self.num_cpus = kwargs.get('num_cpus', 1) 8312337Sjason@lowepower.com self.mem_size = kwargs.get('mem_size', '256MB') 8412337Sjason@lowepower.com self.use_ruby = kwargs.get('use_ruby', False) 8512337Sjason@lowepower.com 8612337Sjason@lowepower.com def create_system(self): 8712337Sjason@lowepower.com sc = SysConfig(None, self.mem_size, None) 8812337Sjason@lowepower.com system = FSConfig.makeArmSystem(self.mem_mode, 8912337Sjason@lowepower.com self.machine_type, self.num_cpus, 9012337Sjason@lowepower.com sc, False, ruby=self.use_ruby) 9112337Sjason@lowepower.com 9212337Sjason@lowepower.com # We typically want the simulator to panic if the kernel 9312337Sjason@lowepower.com # panics or oopses. This prevents the simulator from running 9412337Sjason@lowepower.com # an obviously failed test case until the end of time. 9512337Sjason@lowepower.com system.panic_on_panic = True 9612337Sjason@lowepower.com system.panic_on_oops = True 9712337Sjason@lowepower.com 9812337Sjason@lowepower.com self.init_system(system) 9912337Sjason@lowepower.com return system 10012337Sjason@lowepower.com 10112337Sjason@lowepower.comclass LinuxArmFSSystem(LinuxArmSystemBuilder, 10212337Sjason@lowepower.com BaseFSSystem): 10312337Sjason@lowepower.com """Basic ARM full system builder.""" 104 105 def __init__(self, machine_type='VExpress_EMM', **kwargs): 106 """Initialize an ARM system that supports full system simulation. 107 108 Note: Keyword arguments that are not listed below will be 109 passed to the BaseFSSystem. 110 111 Keyword Arguments: 112 machine_type -- String describing the platform to simulate 113 """ 114 BaseSystem.__init__(self, **kwargs) 115 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 116 117 def create_caches_private(self, cpu): 118 # Use the more representative cache configuration 119 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 120 O3_ARM_v7a_DCache(), 121 O3_ARM_v7aL2()) 122 123class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, 124 BaseFSSystemUniprocessor): 125 """Basic ARM full system builder for uniprocessor systems. 126 127 Note: This class is a specialization of the ArmFSSystem and is 128 only really needed to provide backwards compatibility for existing 129 test cases. 130 """ 131 132 def __init__(self, machine_type='VExpress_EMM', **kwargs): 133 BaseFSSystemUniprocessor.__init__(self, **kwargs) 134 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 135 136class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): 137 """Uniprocessor ARM system prepared for CPU switching""" 138 139 def __init__(self, machine_type='VExpress_EMM', **kwargs): 140 BaseFSSwitcheroo.__init__(self, **kwargs) 141 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 142