arm_generic.py revision 10406:3819b85ff21a 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45from base_config import *
46from O3_ARM_v7a import *
47
48class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
49    """Syscall-emulation builder for ARM uniprocessor systems.
50
51    A small tweak of the syscall-emulation builder to use more
52    representative cache configurations.
53    """
54
55    def __init__(self, **kwargs):
56        BaseSESystem.__init__(self, **kwargs)
57
58    def create_caches_private(self, cpu):
59        # The atomic SE configurations do not use caches
60        if self.mem_mode == "timing":
61            # Use the more representative cache configuration
62            cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
63                                          O3_ARM_v7a_DCache(),
64                                          O3_ARM_v7aL2())
65
66class LinuxArmSystemBuilder(object):
67    """Mix-in that implements create_system.
68
69    This mix-in is intended as a convenient way of adding an
70    ARM-specific create_system method to a class deriving from one of
71    the generic base systems.
72    """
73    def __init__(self, machine_type):
74        """
75        Arguments:
76          machine_type -- String describing the platform to simulate
77        """
78        self.machine_type = machine_type
79
80    def create_system(self):
81        system = FSConfig.makeArmSystem(self.mem_mode,
82                                        self.machine_type, None, False)
83
84        # We typically want the simulator to panic if the kernel
85        # panics or oopses. This prevents the simulator from running
86        # an obviously failed test case until the end of time.
87        system.panic_on_panic = True
88        system.panic_on_oops = True
89
90        self.init_system(system)
91        return system
92
93class LinuxArmFSSystem(LinuxArmSystemBuilder,
94                       BaseFSSystem):
95    """Basic ARM full system builder."""
96
97    def __init__(self, machine_type='RealView_PBX', **kwargs):
98        """Initialize an ARM system that supports full system simulation.
99
100        Note: Keyword arguments that are not listed below will be
101        passed to the BaseFSSystem.
102
103        Keyword Arguments:
104          machine_type -- String describing the platform to simulate
105        """
106        BaseSystem.__init__(self, **kwargs)
107        LinuxArmSystemBuilder.__init__(self, machine_type)
108
109    def create_caches_private(self, cpu):
110        # Use the more representative cache configuration
111        cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
112                                      O3_ARM_v7a_DCache(),
113                                      O3_ARM_v7aL2())
114
115class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
116                                   BaseFSSystemUniprocessor):
117    """Basic ARM full system builder for uniprocessor systems.
118
119    Note: This class is a specialization of the ArmFSSystem and is
120    only really needed to provide backwards compatibility for existing
121    test cases.
122    """
123
124    def __init__(self, machine_type='RealView_PBX', **kwargs):
125        BaseFSSystemUniprocessor.__init__(self, **kwargs)
126        LinuxArmSystemBuilder.__init__(self, machine_type)
127
128class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
129    """Uniprocessor ARM system prepared for CPU switching"""
130
131    def __init__(self, machine_type='RealView_PBX', **kwargs):
132        BaseFSSwitcheroo.__init__(self, **kwargs)
133        LinuxArmSystemBuilder.__init__(self, machine_type)
134