arm_generic.py revision 12097
13569Sgblack@eecs.umich.edu# Copyright (c) 2012, 2017 ARM Limited 23569Sgblack@eecs.umich.edu# All rights reserved. 33569Sgblack@eecs.umich.edu# 43569Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 53569Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 63569Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 73569Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 83569Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93569Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103569Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113569Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123569Sgblack@eecs.umich.edu# 133569Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 143569Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 153569Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 163569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 173569Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 183569Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 193569Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 203569Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 213569Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 223569Sgblack@eecs.umich.edu# this software without specific prior written permission. 233569Sgblack@eecs.umich.edu# 243569Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 253569Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 263569Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 273569Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 283804Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 293569Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 303569Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 313804Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 323811Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 333569Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 343824Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 353811Ssaidi@eecs.umich.edu# 363811Ssaidi@eecs.umich.edu# Authors: Andreas Sandberg 373823Ssaidi@eecs.umich.edu 383823Ssaidi@eecs.umich.edufrom abc import ABCMeta, abstractmethod 393823Ssaidi@eecs.umich.eduimport m5 403569Sgblack@eecs.umich.edufrom m5.objects import * 413569Sgblack@eecs.umich.edufrom m5.proxy import * 423804Ssaidi@eecs.umich.edum5.util.addToPath('../configs/') 433804Ssaidi@eecs.umich.edufrom common import FSConfig 443569Sgblack@eecs.umich.edufrom common.Caches import * 453569Sgblack@eecs.umich.edufrom base_config import * 463569Sgblack@eecs.umich.edufrom common.cores.arm.O3_ARM_v7a import * 473804Ssaidi@eecs.umich.edufrom common.Benchmarks import SysConfig 483881Ssaidi@eecs.umich.edu 493881Ssaidi@eecs.umich.educlass ArmSESystemUniprocessor(BaseSESystemUniprocessor): 503804Ssaidi@eecs.umich.edu """Syscall-emulation builder for ARM uniprocessor systems. 513804Ssaidi@eecs.umich.edu 523804Ssaidi@eecs.umich.edu A small tweak of the syscall-emulation builder to use more 533804Ssaidi@eecs.umich.edu representative cache configurations. 543569Sgblack@eecs.umich.edu """ 553804Ssaidi@eecs.umich.edu 563804Ssaidi@eecs.umich.edu def __init__(self, **kwargs): 573881Ssaidi@eecs.umich.edu BaseSESystem.__init__(self, **kwargs) 583881Ssaidi@eecs.umich.edu 593881Ssaidi@eecs.umich.edu def create_caches_private(self, cpu): 603804Ssaidi@eecs.umich.edu # The atomic SE configurations do not use caches 613569Sgblack@eecs.umich.edu if self.mem_mode == "timing": 623804Ssaidi@eecs.umich.edu # Use the more representative cache configuration 633804Ssaidi@eecs.umich.edu cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 643804Ssaidi@eecs.umich.edu O3_ARM_v7a_DCache(), 653804Ssaidi@eecs.umich.edu O3_ARM_v7aL2()) 663881Ssaidi@eecs.umich.edu 673804Ssaidi@eecs.umich.educlass LinuxArmSystemBuilder(object): 683804Ssaidi@eecs.umich.edu """Mix-in that implements create_system. 693804Ssaidi@eecs.umich.edu 703804Ssaidi@eecs.umich.edu This mix-in is intended as a convenient way of adding an 713804Ssaidi@eecs.umich.edu ARM-specific create_system method to a class deriving from one of 723804Ssaidi@eecs.umich.edu the generic base systems. 733804Ssaidi@eecs.umich.edu """ 743569Sgblack@eecs.umich.edu def __init__(self, machine_type, **kwargs): 753569Sgblack@eecs.umich.edu """ 763804Ssaidi@eecs.umich.edu Arguments: 773804Ssaidi@eecs.umich.edu machine_type -- String describing the platform to simulate 783826Ssaidi@eecs.umich.edu num_cpus -- integer number of CPUs in the system 793804Ssaidi@eecs.umich.edu use_ruby -- True if ruby is used instead of the classic memory system 803569Sgblack@eecs.umich.edu """ 813569Sgblack@eecs.umich.edu self.machine_type = machine_type 823804Ssaidi@eecs.umich.edu self.num_cpus = kwargs.get('num_cpus', 1) 833826Ssaidi@eecs.umich.edu self.mem_size = kwargs.get('mem_size', '256MB') 843907Ssaidi@eecs.umich.edu self.use_ruby = kwargs.get('use_ruby', False) 853826Ssaidi@eecs.umich.edu 863811Ssaidi@eecs.umich.edu def create_system(self): 873836Ssaidi@eecs.umich.edu sc = SysConfig(None, self.mem_size, None) 883915Ssaidi@eecs.umich.edu system = FSConfig.makeArmSystem(self.mem_mode, 893907Ssaidi@eecs.umich.edu self.machine_type, self.num_cpus, 903881Ssaidi@eecs.umich.edu sc, False, ruby=self.use_ruby) 913881Ssaidi@eecs.umich.edu 923881Ssaidi@eecs.umich.edu # We typically want the simulator to panic if the kernel 933881Ssaidi@eecs.umich.edu # panics or oopses. This prevents the simulator from running 943907Ssaidi@eecs.umich.edu # an obviously failed test case until the end of time. 953881Ssaidi@eecs.umich.edu system.panic_on_panic = True 963881Ssaidi@eecs.umich.edu system.panic_on_oops = True 973881Ssaidi@eecs.umich.edu 983881Ssaidi@eecs.umich.edu self.init_system(system) 993881Ssaidi@eecs.umich.edu return system 1003907Ssaidi@eecs.umich.edu 1013907Ssaidi@eecs.umich.educlass LinuxArmFSSystem(LinuxArmSystemBuilder, 1023907Ssaidi@eecs.umich.edu BaseFSSystem): 1033907Ssaidi@eecs.umich.edu """Basic ARM full system builder.""" 1043907Ssaidi@eecs.umich.edu 1053907Ssaidi@eecs.umich.edu def __init__(self, machine_type='VExpress_EMM', **kwargs): 1063907Ssaidi@eecs.umich.edu """Initialize an ARM system that supports full system simulation. 1073907Ssaidi@eecs.umich.edu 1083907Ssaidi@eecs.umich.edu Note: Keyword arguments that are not listed below will be 1093907Ssaidi@eecs.umich.edu passed to the BaseFSSystem. 1103907Ssaidi@eecs.umich.edu 1113907Ssaidi@eecs.umich.edu Keyword Arguments: 1123907Ssaidi@eecs.umich.edu machine_type -- String describing the platform to simulate 1133907Ssaidi@eecs.umich.edu """ 1143907Ssaidi@eecs.umich.edu BaseSystem.__init__(self, **kwargs) 1153907Ssaidi@eecs.umich.edu LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 1163907Ssaidi@eecs.umich.edu 1173907Ssaidi@eecs.umich.edu def create_caches_private(self, cpu): 1183907Ssaidi@eecs.umich.edu # Use the more representative cache configuration 1193907Ssaidi@eecs.umich.edu cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 1203907Ssaidi@eecs.umich.edu O3_ARM_v7a_DCache(), 1213907Ssaidi@eecs.umich.edu O3_ARM_v7aL2()) 1223907Ssaidi@eecs.umich.edu 1233881Ssaidi@eecs.umich.educlass LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, 1243881Ssaidi@eecs.umich.edu BaseFSSystemUniprocessor): 1253881Ssaidi@eecs.umich.edu """Basic ARM full system builder for uniprocessor systems. 1263881Ssaidi@eecs.umich.edu 1273881Ssaidi@eecs.umich.edu Note: This class is a specialization of the ArmFSSystem and is 1283881Ssaidi@eecs.umich.edu only really needed to provide backwards compatibility for existing 1293881Ssaidi@eecs.umich.edu test cases. 1303881Ssaidi@eecs.umich.edu """ 1313881Ssaidi@eecs.umich.edu 1323881Ssaidi@eecs.umich.edu def __init__(self, machine_type='VExpress_EMM', **kwargs): 1333881Ssaidi@eecs.umich.edu BaseFSSystemUniprocessor.__init__(self, **kwargs) 1343881Ssaidi@eecs.umich.edu LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 1353907Ssaidi@eecs.umich.edu 1363811Ssaidi@eecs.umich.educlass LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): 1373826Ssaidi@eecs.umich.edu """Uniprocessor ARM system prepared for CPU switching""" 1383826Ssaidi@eecs.umich.edu 1393826Ssaidi@eecs.umich.edu def __init__(self, machine_type='VExpress_EMM', **kwargs): 1403826Ssaidi@eecs.umich.edu BaseFSSwitcheroo.__init__(self, **kwargs) 1413881Ssaidi@eecs.umich.edu LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 1423881Ssaidi@eecs.umich.edu