ev5_impure.h revision 8013
18012Ssaidi@eecs.umich.edu/* 28013Sbinkertn@umich.edu * Copyright 1993 Hewlett-Packard Development Company, L.P. 38013Sbinkertn@umich.edu * 48013Sbinkertn@umich.edu * Permission is hereby granted, free of charge, to any person 58013Sbinkertn@umich.edu * obtaining a copy of this software and associated documentation 68013Sbinkertn@umich.edu * files (the "Software"), to deal in the Software without 78013Sbinkertn@umich.edu * restriction, including without limitation the rights to use, copy, 88013Sbinkertn@umich.edu * modify, merge, publish, distribute, sublicense, and/or sell copies 98013Sbinkertn@umich.edu * of the Software, and to permit persons to whom the Software is 108013Sbinkertn@umich.edu * furnished to do so, subject to the following conditions: 118013Sbinkertn@umich.edu * 128013Sbinkertn@umich.edu * The above copyright notice and this permission notice shall be 138013Sbinkertn@umich.edu * included in all copies or substantial portions of the Software. 148013Sbinkertn@umich.edu * 158013Sbinkertn@umich.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 168013Sbinkertn@umich.edu * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 178013Sbinkertn@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 188013Sbinkertn@umich.edu * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 198013Sbinkertn@umich.edu * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 208013Sbinkertn@umich.edu * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 218013Sbinkertn@umich.edu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 228013Sbinkertn@umich.edu * SOFTWARE. 238013Sbinkertn@umich.edu */ 248012Ssaidi@eecs.umich.edu 257997Ssaidi@eecs.umich.edu#ifndef EV5_IMPURE_INCLUDED 267997Ssaidi@eecs.umich.edu#define EV5_IMPURE_INCLUDED 277997Ssaidi@eecs.umich.edu 287997Ssaidi@eecs.umich.edu// This uses the Hudson file format from "impure.h" but with the fields from 297997Ssaidi@eecs.umich.edu// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 307997Ssaidi@eecs.umich.edu 318013Sbinkertn@umich.edu// file: impure.sdl 328013Sbinkertn@umich.edu// 338013Sbinkertn@umich.edu// PAL impure scratch area and logout area data structure definitions for 348013Sbinkertn@umich.edu// Alpha firmware. 358013Sbinkertn@umich.edu// 368013Sbinkertn@umich.edu// 378013Sbinkertn@umich.edu// module $pal_impure; 388013Sbinkertn@umich.edu// 398013Sbinkertn@umich.edu// Edit Date Who Description 408013Sbinkertn@umich.edu// ---- --------- --- --------------------- 418013Sbinkertn@umich.edu// 1 7-Jul-93 JEM Initial Entry 428013Sbinkertn@umich.edu// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 438013Sbinkertn@umich.edu// Delete mvptbr 448013Sbinkertn@umich.edu// Calculate pal$logout from end of impure area 458013Sbinkertn@umich.edu// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 468013Sbinkertn@umich.edu// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, 478013Sbinkertn@umich.edu// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, 488013Sbinkertn@umich.edu// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, 498013Sbinkertn@umich.edu// ei_addr, fill_syn, ld_lock 508013Sbinkertn@umich.edu// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be 518013Sbinkertn@umich.edu// consistent with ev4 528013Sbinkertn@umich.edu// add cns$ipr_offset 538013Sbinkertn@umich.edu// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 548013Sbinkertn@umich.edu// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant 558013Sbinkertn@umich.edu// to mchk logout frame 568013Sbinkertn@umich.edu// 578013Sbinkertn@umich.edu// 588013Sbinkertn@umich.edu// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file 597997Ssaidi@eecs.umich.edu//orig 607997Ssaidi@eecs.umich.edu 618013Sbinkertn@umich.edu/* 627997Ssaidi@eecs.umich.edu** Macros for saving/restoring data to/from the PAL impure scratch 637997Ssaidi@eecs.umich.edu** area. 647997Ssaidi@eecs.umich.edu** 657997Ssaidi@eecs.umich.edu** The console save state area is larger than the addressibility 667997Ssaidi@eecs.umich.edu** of the HW_LD/ST instructions (10-bit signed byte displacement), 677997Ssaidi@eecs.umich.edu** so some adjustments to the base offsets, as well as the offsets 687997Ssaidi@eecs.umich.edu** within each base region, are necessary. 697997Ssaidi@eecs.umich.edu** 707997Ssaidi@eecs.umich.edu** The console save state area is divided into two segments; the 717997Ssaidi@eecs.umich.edu** CPU-specific segment and the platform-specific segment. The 727997Ssaidi@eecs.umich.edu** state that is saved in the CPU-specific segment includes GPRs, 737997Ssaidi@eecs.umich.edu** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 747997Ssaidi@eecs.umich.edu** in the platform-specific segment. 757997Ssaidi@eecs.umich.edu** 767997Ssaidi@eecs.umich.edu** The impure pointer will need to be adjusted by a different offset 777997Ssaidi@eecs.umich.edu** value for each region within a given segment. The SAVE and RESTORE 787997Ssaidi@eecs.umich.edu** macros will auto-magically adjust the offsets accordingly. 797997Ssaidi@eecs.umich.edu** 807997Ssaidi@eecs.umich.edu*/ 817997Ssaidi@eecs.umich.edu//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 827997Ssaidi@eecs.umich.edu#define SEXT10(X) ((X) & 0x3ff) 837997Ssaidi@eecs.umich.edu//#define SEXT10(X) (((X) << 55) >> 55) 847997Ssaidi@eecs.umich.edu 857997Ssaidi@eecs.umich.edu#define SAVE_GPR(reg,offset,base) \ 867997Ssaidi@eecs.umich.edu stq_p reg, (SEXT10(offset-0x200))(base) 877997Ssaidi@eecs.umich.edu 887997Ssaidi@eecs.umich.edu#define RESTORE_GPR(reg,offset,base) \ 897997Ssaidi@eecs.umich.edu ldq_p reg, (SEXT10(offset-0x200))(base) 907997Ssaidi@eecs.umich.edu 917997Ssaidi@eecs.umich.edu 927997Ssaidi@eecs.umich.edu#define SAVE_FPR(reg,offset,base) \ 937997Ssaidi@eecs.umich.edu stt reg, (SEXT10(offset-0x200))(base) 947997Ssaidi@eecs.umich.edu 957997Ssaidi@eecs.umich.edu#define RESTORE_FPR(reg,offset,base) \ 967997Ssaidi@eecs.umich.edu ldt reg, (SEXT10(offset-0x200))(base) 977997Ssaidi@eecs.umich.edu 987997Ssaidi@eecs.umich.edu#define SAVE_IPR(reg,offset,base) \ 997997Ssaidi@eecs.umich.edu mfpr v0, reg; \ 1007997Ssaidi@eecs.umich.edu stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) 1017997Ssaidi@eecs.umich.edu 1027997Ssaidi@eecs.umich.edu#define RESTORE_IPR(reg,offset,base) \ 1037997Ssaidi@eecs.umich.edu ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 1047997Ssaidi@eecs.umich.edu mtpr v0, reg 1057997Ssaidi@eecs.umich.edu 1067997Ssaidi@eecs.umich.edu#define SAVE_SHADOW(reg,offset,base) \ 1077997Ssaidi@eecs.umich.edu stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 1087997Ssaidi@eecs.umich.edu 1097997Ssaidi@eecs.umich.edu#define RESTORE_SHADOW(reg,offset,base)\ 1107997Ssaidi@eecs.umich.edu ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 1117997Ssaidi@eecs.umich.edu 1128013Sbinkertn@umich.edu/* Structure of the processor-specific impure area */ 1138013Sbinkertn@umich.edu 1148013Sbinkertn@umich.edu/* aggregate impure struct prefix "" tag ""; 1158013Sbinkertn@umich.edu * cns$flag quadword; 1168013Sbinkertn@umich.edu * cns$hlt quadword; 1178013Sbinkertn@umich.edu */ 1187997Ssaidi@eecs.umich.edu 1197997Ssaidi@eecs.umich.edu/* Define base for debug monitor compatibility */ 1207997Ssaidi@eecs.umich.edu#define CNS_Q_BASE 0x000 1217997Ssaidi@eecs.umich.edu#define CNS_Q_FLAG 0x100 1227997Ssaidi@eecs.umich.edu#define CNS_Q_HALT 0x108 1237997Ssaidi@eecs.umich.edu 1247997Ssaidi@eecs.umich.edu 1258013Sbinkertn@umich.edu/* constant ( 1268013Sbinkertn@umich.edu * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 1278013Sbinkertn@umich.edu * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 1288013Sbinkertn@umich.edu * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 1298013Sbinkertn@umich.edu * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 1308013Sbinkertn@umich.edu * ) equals . increment 8 prefix "" tag ""; 1318013Sbinkertn@umich.edu * cns$gpr quadword dimension 32; 1328013Sbinkertn@umich.edu */ 1338013Sbinkertn@umich.edu 1347997Ssaidi@eecs.umich.edu/* Offset to base of saved GPR area - 32 quadword */ 1357997Ssaidi@eecs.umich.edu#define CNS_Q_GPR 0x110 1367997Ssaidi@eecs.umich.edu#define cns_gpr CNS_Q_GPR 1377997Ssaidi@eecs.umich.edu 1388013Sbinkertn@umich.edu/* constant ( 1398013Sbinkertn@umich.edu * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 1408013Sbinkertn@umich.edu * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 1418013Sbinkertn@umich.edu * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 1428013Sbinkertn@umich.edu * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 1438013Sbinkertn@umich.edu * ) equals . increment 8 prefix "" tag ""; 1448013Sbinkertn@umich.edu * cns$fpr quadword dimension 32; 1458013Sbinkertn@umich.edu */ 1468013Sbinkertn@umich.edu 1477997Ssaidi@eecs.umich.edu/* Offset to base of saved FPR area - 32 quadwords */ 1487997Ssaidi@eecs.umich.edu#define CNS_Q_FPR 0x210 1497997Ssaidi@eecs.umich.edu 1508013Sbinkertn@umich.edu/* #t=.; 1518013Sbinkertn@umich.edu * cns$mchkflag quadword; 1528013Sbinkertn@umich.edu */ 1537997Ssaidi@eecs.umich.edu#define CNS_Q_MCHK 0x310 1547997Ssaidi@eecs.umich.edu 1558013Sbinkertn@umich.edu/* constant cns$pt_offset equals .; 1568013Sbinkertn@umich.edu * constant ( 1578013Sbinkertn@umich.edu * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 1588013Sbinkertn@umich.edu * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 1598013Sbinkertn@umich.edu * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 1608013Sbinkertn@umich.edu * cns$pt21,cns$pt22,cns$pt23 1618013Sbinkertn@umich.edu * ) equals . increment 8 prefix "" tag ""; 1628013Sbinkertn@umich.edu * cns$pt quadword dimension 24; 1638013Sbinkertn@umich.edu */ 1647997Ssaidi@eecs.umich.edu/* Offset to base of saved PALtemp area - 25 quadwords */ 1657997Ssaidi@eecs.umich.edu#define CNS_Q_PT 0x318 1667997Ssaidi@eecs.umich.edu 1678013Sbinkertn@umich.edu/* cns$shadow8 quadword; 1688013Sbinkertn@umich.edu * cns$shadow9 quadword; 1698013Sbinkertn@umich.edu * cns$shadow10 quadword; 1708013Sbinkertn@umich.edu * cns$shadow11 quadword; 1718013Sbinkertn@umich.edu * cns$shadow12 quadword; 1728013Sbinkertn@umich.edu * cns$shadow13 quadword; 1738013Sbinkertn@umich.edu * cns$shadow14 quadword; 1748013Sbinkertn@umich.edu * cns$shadow25 quadword; 1758013Sbinkertn@umich.edu */ 1767997Ssaidi@eecs.umich.edu/* Offset to base of saved PALshadow area - 8 quadwords */ 1777997Ssaidi@eecs.umich.edu#define CNS_Q_SHADOW 0x3D8 1787997Ssaidi@eecs.umich.edu 1797997Ssaidi@eecs.umich.edu/* Offset to base of saved IPR area */ 1807997Ssaidi@eecs.umich.edu#define CNS_Q_IPR 0x418 1817997Ssaidi@eecs.umich.edu 1828013Sbinkertn@umich.edu/* constant cns$ipr_offset equals .; */ 1838013Sbinkertn@umich.edu/* cns$exc_addr quadword; */ 1847997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_ADDR 0x418 1858013Sbinkertn@umich.edu/* cns$pal_base quadword; */ 1867997Ssaidi@eecs.umich.edu#define CNS_Q_PAL_BASE 0x420 1878013Sbinkertn@umich.edu/* cns$mm_stat quadword; */ 1887997Ssaidi@eecs.umich.edu#define CNS_Q_MM_STAT 0x428 1898013Sbinkertn@umich.edu/* cns$va quadword; */ 1907997Ssaidi@eecs.umich.edu#define CNS_Q_VA 0x430 1918013Sbinkertn@umich.edu/* cns$icsr quadword; */ 1927997Ssaidi@eecs.umich.edu#define CNS_Q_ICSR 0x438 1938013Sbinkertn@umich.edu/* cns$ipl quadword; */ 1947997Ssaidi@eecs.umich.edu#define CNS_Q_IPL 0x440 1958013Sbinkertn@umich.edu/* cns$ps quadword; // Ibox current mode */ 1967997Ssaidi@eecs.umich.edu#define CNS_Q_IPS 0x448 1978013Sbinkertn@umich.edu/* cns$itb_asn quadword; */ 1987997Ssaidi@eecs.umich.edu#define CNS_Q_ITB_ASN 0x450 1998013Sbinkertn@umich.edu/* cns$aster quadword; */ 2007997Ssaidi@eecs.umich.edu#define CNS_Q_ASTER 0x458 2018013Sbinkertn@umich.edu/* cns$astrr quadword; */ 2027997Ssaidi@eecs.umich.edu#define CNS_Q_ASTRR 0x460 2038013Sbinkertn@umich.edu/* cns$isr quadword; */ 2047997Ssaidi@eecs.umich.edu#define CNS_Q_ISR 0x468 2058013Sbinkertn@umich.edu/* cns$ivptbr quadword; */ 2067997Ssaidi@eecs.umich.edu#define CNS_Q_IVPTBR 0x470 2078013Sbinkertn@umich.edu/* cns$mcsr quadword; */ 2087997Ssaidi@eecs.umich.edu#define CNS_Q_MCSR 0x478 2098013Sbinkertn@umich.edu/* cns$dc_mode quadword; */ 2107997Ssaidi@eecs.umich.edu#define CNS_Q_DC_MODE 0x480 2118013Sbinkertn@umich.edu/* cns$maf_mode quadword; */ 2127997Ssaidi@eecs.umich.edu#define CNS_Q_MAF_MODE 0x488 2138013Sbinkertn@umich.edu/* cns$sirr quadword; */ 2147997Ssaidi@eecs.umich.edu#define CNS_Q_SIRR 0x490 2158013Sbinkertn@umich.edu/* cns$fpcsr quadword; */ 2167997Ssaidi@eecs.umich.edu#define CNS_Q_FPCSR 0x498 2178013Sbinkertn@umich.edu/* cns$icperr_stat quadword; */ 2187997Ssaidi@eecs.umich.edu#define CNS_Q_ICPERR_STAT 0x4A0 2198013Sbinkertn@umich.edu/* cns$pmctr quadword; */ 2207997Ssaidi@eecs.umich.edu#define CNS_Q_PM_CTR 0x4A8 2218013Sbinkertn@umich.edu/* cns$exc_sum quadword; */ 2227997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_SUM 0x4B0 2238013Sbinkertn@umich.edu/* cns$exc_mask quadword; */ 2247997Ssaidi@eecs.umich.edu#define CNS_Q_EXC_MASK 0x4B8 2258013Sbinkertn@umich.edu/* cns$intid quadword; */ 2267997Ssaidi@eecs.umich.edu#define CNS_Q_INT_ID 0x4C0 2278013Sbinkertn@umich.edu/* cns$dcperr_stat quadword; */ 2287997Ssaidi@eecs.umich.edu#define CNS_Q_DCPERR_STAT 0x4C8 2298013Sbinkertn@umich.edu/* cns$sc_stat quadword; */ 2307997Ssaidi@eecs.umich.edu#define CNS_Q_SC_STAT 0x4D0 2318013Sbinkertn@umich.edu/* cns$sc_addr quadword; */ 2327997Ssaidi@eecs.umich.edu#define CNS_Q_SC_ADDR 0x4D8 2338013Sbinkertn@umich.edu/* cns$sc_ctl quadword; */ 2347997Ssaidi@eecs.umich.edu#define CNS_Q_SC_CTL 0x4E0 2358013Sbinkertn@umich.edu/* cns$bc_tag_addr quadword; */ 2367997Ssaidi@eecs.umich.edu#define CNS_Q_BC_TAG_ADDR 0x4E8 2378013Sbinkertn@umich.edu/* cns$ei_stat quadword; */ 2387997Ssaidi@eecs.umich.edu#define CNS_Q_EI_STAT 0x4F0 2398013Sbinkertn@umich.edu/* cns$ei_addr quadword; */ 2407997Ssaidi@eecs.umich.edu#define CNS_Q_EI_ADDR 0x4F8 2418013Sbinkertn@umich.edu/* cns$fill_syn quadword; */ 2427997Ssaidi@eecs.umich.edu#define CNS_Q_FILL_SYN 0x500 2438013Sbinkertn@umich.edu/* cns$ld_lock quadword; */ 2447997Ssaidi@eecs.umich.edu#define CNS_Q_LD_LOCK 0x508 2458013Sbinkertn@umich.edu/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ 2467997Ssaidi@eecs.umich.edu#define CNS_Q_BC_CTL 0x510 2478013Sbinkertn@umich.edu/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ 2487997Ssaidi@eecs.umich.edu#define CNS_Q_PM_CTL 0x518 2498013Sbinkertn@umich.edu/* cns$bc_config quadword; // shadow of on chip bc_config */ 2507997Ssaidi@eecs.umich.edu#define CNS_Q_BC_CFG 0x520 2517997Ssaidi@eecs.umich.edu 2528013Sbinkertn@umich.edu/* constant cns$size equals .; 2538013Sbinkertn@umich.edu * 2548013Sbinkertn@umich.edu * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 2558013Sbinkertn@umich.edu * constant pal$impure_specific_size equals (.+7) & %xfff8; 2568013Sbinkertn@umich.edu * constant cns$mchksize equals (.+7-#t) & %xfff8; 2578013Sbinkertn@umich.edu * constant pal$logout_area equals pal$impure_specific_size ; 2588013Sbinkertn@umich.edu * end impure; 2597997Ssaidi@eecs.umich.edu*/ 2607997Ssaidi@eecs.umich.edu 2617997Ssaidi@eecs.umich.edu/* This next set of stuff came from the old code ..pb */ 2627997Ssaidi@eecs.umich.edu#define CNS_Q_SROM_REV 0x528 2637997Ssaidi@eecs.umich.edu#define CNS_Q_PROC_ID 0x530 2647997Ssaidi@eecs.umich.edu#define CNS_Q_MEM_SIZE 0x538 2657997Ssaidi@eecs.umich.edu#define CNS_Q_CYCLE_CNT 0x540 2667997Ssaidi@eecs.umich.edu#define CNS_Q_SIGNATURE 0x548 2677997Ssaidi@eecs.umich.edu#define CNS_Q_PROC_MASK 0x550 2687997Ssaidi@eecs.umich.edu#define CNS_Q_SYSCTX 0x558 2697997Ssaidi@eecs.umich.edu 2707997Ssaidi@eecs.umich.edu 2717997Ssaidi@eecs.umich.edu 2727997Ssaidi@eecs.umich.edu#define MACHINE_CHECK_CRD_BASE 0 2737997Ssaidi@eecs.umich.edu#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 2747997Ssaidi@eecs.umich.edu 2757997Ssaidi@eecs.umich.edu 2767997Ssaidi@eecs.umich.edu 2778013Sbinkertn@umich.edu/* 2788013Sbinkertn@umich.edu * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 2798013Sbinkertn@umich.edu * SPROCESS bitfield length 1 ; 2808013Sbinkertn@umich.edu * FILL_0 bitfield length 3 fill tag $$; 2818013Sbinkertn@umich.edu * FRQ2 bitfield length 2 ; 2828013Sbinkertn@umich.edu * FRQ1 bitfield length 2 ; 2838013Sbinkertn@umich.edu * FRQ0 bitfield length 2 ; 2848013Sbinkertn@umich.edu * CTL2 bitfield length 2 ; 2858013Sbinkertn@umich.edu * CTL1 bitfield length 2 ; 2868013Sbinkertn@umich.edu * CTL0 bitfield length 2 ; 2878013Sbinkertn@umich.edu * FILL_1 bitfield length 16 fill tag $$; 2888013Sbinkertn@umich.edu * FILL_2 bitfield length 32 fill tag $$; 2898013Sbinkertn@umich.edu * end EV5PMCTRCTL_BITS; 2908013Sbinkertn@umich.edu * 2918013Sbinkertn@umich.edu * end_module $pal_impure; 2928013Sbinkertn@umich.edu * 2938013Sbinkertn@umich.edu * module $pal_logout; 2948013Sbinkertn@umich.edu * 2958013Sbinkertn@umich.edu * // 2968013Sbinkertn@umich.edu * // Start definition of Corrected Error Frame 2978013Sbinkertn@umich.edu * // 2987997Ssaidi@eecs.umich.edu */ 2997997Ssaidi@eecs.umich.edu 3007997Ssaidi@eecs.umich.edu/* 3018013Sbinkertn@umich.edu * aggregate crd_logout struct prefix "" tag ""; 3027997Ssaidi@eecs.umich.edu */ 3037997Ssaidi@eecs.umich.edu 3047997Ssaidi@eecs.umich.edu#define pal_logout_area 0x600 3057997Ssaidi@eecs.umich.edu#define mchk_crd_base 0 3067997Ssaidi@eecs.umich.edu 3078013Sbinkertn@umich.edu/* mchk$crd_flag quadword; */ 3087997Ssaidi@eecs.umich.edu#define mchk_crd_flag 0 3098013Sbinkertn@umich.edu/* mchk$crd_offsets quadword; */ 3107997Ssaidi@eecs.umich.edu#define mchk_crd_offsets 8 3118013Sbinkertn@umich.edu/* 3128013Sbinkertn@umich.edu * // Pal-specific information */ 3137997Ssaidi@eecs.umich.edu#define mchk_crd_mchk_code 0x10 3148013Sbinkertn@umich.edu/* mchk$crd_mchk_code quadword; 3158013Sbinkertn@umich.edu * 3168013Sbinkertn@umich.edu * // CPU-specific information 3178013Sbinkertn@umich.edu * constant mchk$crd_cpu_base equals . ; 3188013Sbinkertn@umich.edu * mchk$crd_ei_addr quadword; */ 3197997Ssaidi@eecs.umich.edu#define mchk_crd_ei_addr 0x18 3208013Sbinkertn@umich.edu/* mchk$crd_fill_syn quadword; */ 3217997Ssaidi@eecs.umich.edu#define mchk_crd_fill_syn 0x20 3228013Sbinkertn@umich.edu/* mchk$crd_ei_stat quadword; */ 3237997Ssaidi@eecs.umich.edu#define mchk_crd_ei_stat 0x28 3248013Sbinkertn@umich.edu/* mchk$crd_isr quadword; */ 3257997Ssaidi@eecs.umich.edu#define mchk_crd_isr 0x30 3267997Ssaidi@eecs.umich.edu 3277997Ssaidi@eecs.umich.edu/* 3287997Ssaidi@eecs.umich.edu * Hacked up constants for the turbolaser build. Hope 3297997Ssaidi@eecs.umich.edu * this is moreless correct 3307997Ssaidi@eecs.umich.edu */ 3317997Ssaidi@eecs.umich.edu 3327997Ssaidi@eecs.umich.edu#define mchk_crd_whami 0x38 3337997Ssaidi@eecs.umich.edu#define mchk_crd_tldev 0x40 3347997Ssaidi@eecs.umich.edu#define mchk_crd_tlber 0x48 3357997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr0 0x50 3367997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr1 0x58 3377997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr2 0x60 3387997Ssaidi@eecs.umich.edu#define mchk_crd_tlesr3 0x68 3397997Ssaidi@eecs.umich.edu#define mchk_crd_rsvd 0x70 3407997Ssaidi@eecs.umich.edu 3417997Ssaidi@eecs.umich.edu 3427997Ssaidi@eecs.umich.edu/* 3437997Ssaidi@eecs.umich.edu * mchk area seems different for tlaser 3447997Ssaidi@eecs.umich.edu */ 3457997Ssaidi@eecs.umich.edu 3467997Ssaidi@eecs.umich.edu#define mchk_crd_size 0x80 3477997Ssaidi@eecs.umich.edu#define mchk_mchk_base (mchk_crd_size) 3487997Ssaidi@eecs.umich.edu 3497997Ssaidi@eecs.umich.edu#define mchk_tlber 0x0 3507997Ssaidi@eecs.umich.edu#define mchk_tlepaerr 0x8 3517997Ssaidi@eecs.umich.edu#define mchk_tlepderr 0x10 3527997Ssaidi@eecs.umich.edu#define mchk_tlepmerr 0x18 3537997Ssaidi@eecs.umich.edu 3547997Ssaidi@eecs.umich.edu 3558013Sbinkertn@umich.edu/* 3568013Sbinkertn@umich.edu * // System-specific information 3578013Sbinkertn@umich.edu * constant mchk$crd_sys_base equals . ; 3588013Sbinkertn@umich.edu * constant mchk$crd_size equals (.+7) & %xfff8; 3598013Sbinkertn@umich.edu * 3608013Sbinkertn@umich.edu * end crd_logout; 3618013Sbinkertn@umich.edu * // 3628013Sbinkertn@umich.edu * // Start definition of Machine check logout Frame 3638013Sbinkertn@umich.edu * // 3648013Sbinkertn@umich.edu * aggregate logout struct prefix "" tag ""; 3658013Sbinkertn@umich.edu * mchk$flag quadword; */ 3668013Sbinkertn@umich.edu/* mchk$offsets quadword; */ 3678013Sbinkertn@umich.edu/* 3688013Sbinkertn@umich.edu * // Pal-specific information 3698013Sbinkertn@umich.edu * mchk$mchk_code quadword; */ 3707997Ssaidi@eecs.umich.edu/* 3717997Ssaidi@eecs.umich.edu 3728013Sbinkertn@umich.edu * mchk$pt quadword dimension 24; 3738013Sbinkertn@umich.edu * 3748013Sbinkertn@umich.edu * // CPU-specific information 3758013Sbinkertn@umich.edu * constant mchk$cpu_base equals . ; 3768013Sbinkertn@umich.edu * mchk$exc_addr quadword; 3778013Sbinkertn@umich.edu * mchk$exc_sum quadword; 3788013Sbinkertn@umich.edu * mchk$exc_mask quadword; 3798013Sbinkertn@umich.edu * mchk$pal_base quadword; 3808013Sbinkertn@umich.edu * mchk$isr quadword; 3818013Sbinkertn@umich.edu * mchk$icsr quadword; 3828013Sbinkertn@umich.edu * mchk$ic_perr_stat quadword; 3838013Sbinkertn@umich.edu * mchk$dc_perr_stat quadword; 3848013Sbinkertn@umich.edu * mchk$va quadword; 3858013Sbinkertn@umich.edu * mchk$mm_stat quadword; 3868013Sbinkertn@umich.edu * mchk$sc_addr quadword; 3878013Sbinkertn@umich.edu * mchk$sc_stat quadword; 3888013Sbinkertn@umich.edu * mchk$bc_tag_addr quadword; 3898013Sbinkertn@umich.edu * mchk$ei_addr quadword; 3908013Sbinkertn@umich.edu * mchk$fill_syn quadword; 3918013Sbinkertn@umich.edu * mchk$ei_stat quadword; 3928013Sbinkertn@umich.edu * mchk$ld_lock quadword; 3938013Sbinkertn@umich.edu * 3948013Sbinkertn@umich.edu * // System-specific information 3958013Sbinkertn@umich.edu * 3968013Sbinkertn@umich.edu * constant mchk$sys_base equals . ; 3978013Sbinkertn@umich.edu * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 3988013Sbinkertn@umich.edu * 3998013Sbinkertn@umich.edu * constant mchk$size equals (.+7) & %xfff8; 4008013Sbinkertn@umich.edu * 4018013Sbinkertn@umich.edu * 4028013Sbinkertn@umich.edu * constant mchk$crd_base equals 0 ; 4038013Sbinkertn@umich.edu * constant mchk$mchk_base equals mchk$crd_size ; 4048013Sbinkertn@umich.edu * 4058013Sbinkertn@umich.edu * 4068013Sbinkertn@umich.edu * end logout; 4078013Sbinkertn@umich.edu * 4088013Sbinkertn@umich.edu * end_module $pal_logout; 4097997Ssaidi@eecs.umich.edu*/ 4107997Ssaidi@eecs.umich.edu 4118013Sbinkertn@umich.edu/* 4128013Sbinkertn@umich.edu * this is lingering in the old ladbx code but looks like it was from 4138013Sbinkertn@umich.edu * ev4 days. This was 0x160 in the old days..pb 4148013Sbinkertn@umich.edu */ 4157997Ssaidi@eecs.umich.edu#define LAF_K_SIZE MACHINE_CHECK_SIZE 4167997Ssaidi@eecs.umich.edu#endif 417