ev5_impure.h revision 8013
1/* 2 * Copyright 1993 Hewlett-Packard Development Company, L.P. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#ifndef EV5_IMPURE_INCLUDED 26#define EV5_IMPURE_INCLUDED 27 28// This uses the Hudson file format from "impure.h" but with the fields from 29// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 30 31// file: impure.sdl 32// 33// PAL impure scratch area and logout area data structure definitions for 34// Alpha firmware. 35// 36// 37// module $pal_impure; 38// 39// Edit Date Who Description 40// ---- --------- --- --------------------- 41// 1 7-Jul-93 JEM Initial Entry 42// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area 43// Delete mvptbr 44// Calculate pal$logout from end of impure area 45// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions 46// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, 47// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, 48// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, 49// ei_addr, fill_syn, ld_lock 50// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be 51// consistent with ev4 52// add cns$ipr_offset 53// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. 54// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant 55// to mchk logout frame 56// 57// 58// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file 59//orig 60 61/* 62** Macros for saving/restoring data to/from the PAL impure scratch 63** area. 64** 65** The console save state area is larger than the addressibility 66** of the HW_LD/ST instructions (10-bit signed byte displacement), 67** so some adjustments to the base offsets, as well as the offsets 68** within each base region, are necessary. 69** 70** The console save state area is divided into two segments; the 71** CPU-specific segment and the platform-specific segment. The 72** state that is saved in the CPU-specific segment includes GPRs, 73** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved 74** in the platform-specific segment. 75** 76** The impure pointer will need to be adjusted by a different offset 77** value for each region within a given segment. The SAVE and RESTORE 78** macros will auto-magically adjust the offsets accordingly. 79** 80*/ 81//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) 82#define SEXT10(X) ((X) & 0x3ff) 83//#define SEXT10(X) (((X) << 55) >> 55) 84 85#define SAVE_GPR(reg,offset,base) \ 86 stq_p reg, (SEXT10(offset-0x200))(base) 87 88#define RESTORE_GPR(reg,offset,base) \ 89 ldq_p reg, (SEXT10(offset-0x200))(base) 90 91 92#define SAVE_FPR(reg,offset,base) \ 93 stt reg, (SEXT10(offset-0x200))(base) 94 95#define RESTORE_FPR(reg,offset,base) \ 96 ldt reg, (SEXT10(offset-0x200))(base) 97 98#define SAVE_IPR(reg,offset,base) \ 99 mfpr v0, reg; \ 100 stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) 101 102#define RESTORE_IPR(reg,offset,base) \ 103 ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ 104 mtpr v0, reg 105 106#define SAVE_SHADOW(reg,offset,base) \ 107 stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 108 109#define RESTORE_SHADOW(reg,offset,base)\ 110 ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) 111 112/* Structure of the processor-specific impure area */ 113 114/* aggregate impure struct prefix "" tag ""; 115 * cns$flag quadword; 116 * cns$hlt quadword; 117 */ 118 119/* Define base for debug monitor compatibility */ 120#define CNS_Q_BASE 0x000 121#define CNS_Q_FLAG 0x100 122#define CNS_Q_HALT 0x108 123 124 125/* constant ( 126 * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, 127 * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, 128 * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, 129 * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 130 * ) equals . increment 8 prefix "" tag ""; 131 * cns$gpr quadword dimension 32; 132 */ 133 134/* Offset to base of saved GPR area - 32 quadword */ 135#define CNS_Q_GPR 0x110 136#define cns_gpr CNS_Q_GPR 137 138/* constant ( 139 * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, 140 * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, 141 * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, 142 * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 143 * ) equals . increment 8 prefix "" tag ""; 144 * cns$fpr quadword dimension 32; 145 */ 146 147/* Offset to base of saved FPR area - 32 quadwords */ 148#define CNS_Q_FPR 0x210 149 150/* #t=.; 151 * cns$mchkflag quadword; 152 */ 153#define CNS_Q_MCHK 0x310 154 155/* constant cns$pt_offset equals .; 156 * constant ( 157 * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, 158 * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, 159 * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, 160 * cns$pt21,cns$pt22,cns$pt23 161 * ) equals . increment 8 prefix "" tag ""; 162 * cns$pt quadword dimension 24; 163 */ 164/* Offset to base of saved PALtemp area - 25 quadwords */ 165#define CNS_Q_PT 0x318 166 167/* cns$shadow8 quadword; 168 * cns$shadow9 quadword; 169 * cns$shadow10 quadword; 170 * cns$shadow11 quadword; 171 * cns$shadow12 quadword; 172 * cns$shadow13 quadword; 173 * cns$shadow14 quadword; 174 * cns$shadow25 quadword; 175 */ 176/* Offset to base of saved PALshadow area - 8 quadwords */ 177#define CNS_Q_SHADOW 0x3D8 178 179/* Offset to base of saved IPR area */ 180#define CNS_Q_IPR 0x418 181 182/* constant cns$ipr_offset equals .; */ 183/* cns$exc_addr quadword; */ 184#define CNS_Q_EXC_ADDR 0x418 185/* cns$pal_base quadword; */ 186#define CNS_Q_PAL_BASE 0x420 187/* cns$mm_stat quadword; */ 188#define CNS_Q_MM_STAT 0x428 189/* cns$va quadword; */ 190#define CNS_Q_VA 0x430 191/* cns$icsr quadword; */ 192#define CNS_Q_ICSR 0x438 193/* cns$ipl quadword; */ 194#define CNS_Q_IPL 0x440 195/* cns$ps quadword; // Ibox current mode */ 196#define CNS_Q_IPS 0x448 197/* cns$itb_asn quadword; */ 198#define CNS_Q_ITB_ASN 0x450 199/* cns$aster quadword; */ 200#define CNS_Q_ASTER 0x458 201/* cns$astrr quadword; */ 202#define CNS_Q_ASTRR 0x460 203/* cns$isr quadword; */ 204#define CNS_Q_ISR 0x468 205/* cns$ivptbr quadword; */ 206#define CNS_Q_IVPTBR 0x470 207/* cns$mcsr quadword; */ 208#define CNS_Q_MCSR 0x478 209/* cns$dc_mode quadword; */ 210#define CNS_Q_DC_MODE 0x480 211/* cns$maf_mode quadword; */ 212#define CNS_Q_MAF_MODE 0x488 213/* cns$sirr quadword; */ 214#define CNS_Q_SIRR 0x490 215/* cns$fpcsr quadword; */ 216#define CNS_Q_FPCSR 0x498 217/* cns$icperr_stat quadword; */ 218#define CNS_Q_ICPERR_STAT 0x4A0 219/* cns$pmctr quadword; */ 220#define CNS_Q_PM_CTR 0x4A8 221/* cns$exc_sum quadword; */ 222#define CNS_Q_EXC_SUM 0x4B0 223/* cns$exc_mask quadword; */ 224#define CNS_Q_EXC_MASK 0x4B8 225/* cns$intid quadword; */ 226#define CNS_Q_INT_ID 0x4C0 227/* cns$dcperr_stat quadword; */ 228#define CNS_Q_DCPERR_STAT 0x4C8 229/* cns$sc_stat quadword; */ 230#define CNS_Q_SC_STAT 0x4D0 231/* cns$sc_addr quadword; */ 232#define CNS_Q_SC_ADDR 0x4D8 233/* cns$sc_ctl quadword; */ 234#define CNS_Q_SC_CTL 0x4E0 235/* cns$bc_tag_addr quadword; */ 236#define CNS_Q_BC_TAG_ADDR 0x4E8 237/* cns$ei_stat quadword; */ 238#define CNS_Q_EI_STAT 0x4F0 239/* cns$ei_addr quadword; */ 240#define CNS_Q_EI_ADDR 0x4F8 241/* cns$fill_syn quadword; */ 242#define CNS_Q_FILL_SYN 0x500 243/* cns$ld_lock quadword; */ 244#define CNS_Q_LD_LOCK 0x508 245/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ 246#define CNS_Q_BC_CTL 0x510 247/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ 248#define CNS_Q_PM_CTL 0x518 249/* cns$bc_config quadword; // shadow of on chip bc_config */ 250#define CNS_Q_BC_CFG 0x520 251 252/* constant cns$size equals .; 253 * 254 * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; 255 * constant pal$impure_specific_size equals (.+7) & %xfff8; 256 * constant cns$mchksize equals (.+7-#t) & %xfff8; 257 * constant pal$logout_area equals pal$impure_specific_size ; 258 * end impure; 259*/ 260 261/* This next set of stuff came from the old code ..pb */ 262#define CNS_Q_SROM_REV 0x528 263#define CNS_Q_PROC_ID 0x530 264#define CNS_Q_MEM_SIZE 0x538 265#define CNS_Q_CYCLE_CNT 0x540 266#define CNS_Q_SIGNATURE 0x548 267#define CNS_Q_PROC_MASK 0x550 268#define CNS_Q_SYSCTX 0x558 269 270 271 272#define MACHINE_CHECK_CRD_BASE 0 273#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) 274 275 276 277/* 278 * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; 279 * SPROCESS bitfield length 1 ; 280 * FILL_0 bitfield length 3 fill tag $$; 281 * FRQ2 bitfield length 2 ; 282 * FRQ1 bitfield length 2 ; 283 * FRQ0 bitfield length 2 ; 284 * CTL2 bitfield length 2 ; 285 * CTL1 bitfield length 2 ; 286 * CTL0 bitfield length 2 ; 287 * FILL_1 bitfield length 16 fill tag $$; 288 * FILL_2 bitfield length 32 fill tag $$; 289 * end EV5PMCTRCTL_BITS; 290 * 291 * end_module $pal_impure; 292 * 293 * module $pal_logout; 294 * 295 * // 296 * // Start definition of Corrected Error Frame 297 * // 298 */ 299 300/* 301 * aggregate crd_logout struct prefix "" tag ""; 302 */ 303 304#define pal_logout_area 0x600 305#define mchk_crd_base 0 306 307/* mchk$crd_flag quadword; */ 308#define mchk_crd_flag 0 309/* mchk$crd_offsets quadword; */ 310#define mchk_crd_offsets 8 311/* 312 * // Pal-specific information */ 313#define mchk_crd_mchk_code 0x10 314/* mchk$crd_mchk_code quadword; 315 * 316 * // CPU-specific information 317 * constant mchk$crd_cpu_base equals . ; 318 * mchk$crd_ei_addr quadword; */ 319#define mchk_crd_ei_addr 0x18 320/* mchk$crd_fill_syn quadword; */ 321#define mchk_crd_fill_syn 0x20 322/* mchk$crd_ei_stat quadword; */ 323#define mchk_crd_ei_stat 0x28 324/* mchk$crd_isr quadword; */ 325#define mchk_crd_isr 0x30 326 327/* 328 * Hacked up constants for the turbolaser build. Hope 329 * this is moreless correct 330 */ 331 332#define mchk_crd_whami 0x38 333#define mchk_crd_tldev 0x40 334#define mchk_crd_tlber 0x48 335#define mchk_crd_tlesr0 0x50 336#define mchk_crd_tlesr1 0x58 337#define mchk_crd_tlesr2 0x60 338#define mchk_crd_tlesr3 0x68 339#define mchk_crd_rsvd 0x70 340 341 342/* 343 * mchk area seems different for tlaser 344 */ 345 346#define mchk_crd_size 0x80 347#define mchk_mchk_base (mchk_crd_size) 348 349#define mchk_tlber 0x0 350#define mchk_tlepaerr 0x8 351#define mchk_tlepderr 0x10 352#define mchk_tlepmerr 0x18 353 354 355/* 356 * // System-specific information 357 * constant mchk$crd_sys_base equals . ; 358 * constant mchk$crd_size equals (.+7) & %xfff8; 359 * 360 * end crd_logout; 361 * // 362 * // Start definition of Machine check logout Frame 363 * // 364 * aggregate logout struct prefix "" tag ""; 365 * mchk$flag quadword; */ 366/* mchk$offsets quadword; */ 367/* 368 * // Pal-specific information 369 * mchk$mchk_code quadword; */ 370/* 371 372 * mchk$pt quadword dimension 24; 373 * 374 * // CPU-specific information 375 * constant mchk$cpu_base equals . ; 376 * mchk$exc_addr quadword; 377 * mchk$exc_sum quadword; 378 * mchk$exc_mask quadword; 379 * mchk$pal_base quadword; 380 * mchk$isr quadword; 381 * mchk$icsr quadword; 382 * mchk$ic_perr_stat quadword; 383 * mchk$dc_perr_stat quadword; 384 * mchk$va quadword; 385 * mchk$mm_stat quadword; 386 * mchk$sc_addr quadword; 387 * mchk$sc_stat quadword; 388 * mchk$bc_tag_addr quadword; 389 * mchk$ei_addr quadword; 390 * mchk$fill_syn quadword; 391 * mchk$ei_stat quadword; 392 * mchk$ld_lock quadword; 393 * 394 * // System-specific information 395 * 396 * constant mchk$sys_base equals . ; 397 * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff 398 * 399 * constant mchk$size equals (.+7) & %xfff8; 400 * 401 * 402 * constant mchk$crd_base equals 0 ; 403 * constant mchk$mchk_base equals mchk$crd_size ; 404 * 405 * 406 * end logout; 407 * 408 * end_module $pal_logout; 409*/ 410 411/* 412 * this is lingering in the old ladbx code but looks like it was from 413 * ev4 days. This was 0x160 in the old days..pb 414 */ 415#define LAF_K_SIZE MACHINE_CHECK_SIZE 416#endif 417