ev5_defs.h revision 7997
17997Ssaidi@eecs.umich.edu#ifndef EV5_DEFS_INCLUDED 27997Ssaidi@eecs.umich.edu#define EV5_DEFS_INCLUDED 1 37997Ssaidi@eecs.umich.edu 47997Ssaidi@eecs.umich.edu// adapted from the version emailed to lance..pb Nov/95 57997Ssaidi@eecs.umich.edu 67997Ssaidi@eecs.umich.edu 77997Ssaidi@eecs.umich.edu// ******************************************************************************************************************************** 87997Ssaidi@eecs.umich.edu// Created 25-JUL-1995 14:21:23 by VAX SDL V3.2-12 Source: 21-JUL-1995 11:03:08 EV5$:[EV5.DVT.SUP]EV5_DEFS.SDL;24 97997Ssaidi@eecs.umich.edu// ******************************************************************************************************************************** 107997Ssaidi@eecs.umich.edu 117997Ssaidi@eecs.umich.edu// .MACRO $EV5DEF,..EQU=<=>,..COL=<:> 127997Ssaidi@eecs.umich.edu// EV5$K_REVISION'..equ'34 137997Ssaidi@eecs.umich.edu// In the definitions below, registers are annotated with one of the following 147997Ssaidi@eecs.umich.edu// symbols: 157997Ssaidi@eecs.umich.edu// 167997Ssaidi@eecs.umich.edu// RW - The register may be read and written 177997Ssaidi@eecs.umich.edu// RO - The register may only be read 187997Ssaidi@eecs.umich.edu// WO - The register may only be written 197997Ssaidi@eecs.umich.edu// 207997Ssaidi@eecs.umich.edu// For RO and WO registers, all bits and fields within the register are also 217997Ssaidi@eecs.umich.edu// read-only or write-only. For RW registers, each bit or field within 227997Ssaidi@eecs.umich.edu// the register is annotated with one of the following: 237997Ssaidi@eecs.umich.edu// 247997Ssaidi@eecs.umich.edu// RW - The bit/field may be read and written 257997Ssaidi@eecs.umich.edu// RO - The bit/field may be read; writes are ignored 267997Ssaidi@eecs.umich.edu// WO - The bit/field may be written; reads return an UNPREDICTABLE result. 277997Ssaidi@eecs.umich.edu// WZ - The bit/field may be written; reads return a 0 287997Ssaidi@eecs.umich.edu// WC - The bit/field may be read; writes cause state to clear 297997Ssaidi@eecs.umich.edu// RC - The bit/field may be read, which also causes state to clear; writes are ignored 307997Ssaidi@eecs.umich.edu// Architecturally-defined (SRM) registers for EVMS 317997Ssaidi@eecs.umich.edu#define pt0 320 327997Ssaidi@eecs.umich.edu#define pt1 321 337997Ssaidi@eecs.umich.edu#define pt2 322 347997Ssaidi@eecs.umich.edu#define pt3 323 357997Ssaidi@eecs.umich.edu#define pt4 324 367997Ssaidi@eecs.umich.edu#define pt5 325 377997Ssaidi@eecs.umich.edu#define pt6 326 387997Ssaidi@eecs.umich.edu#define pt7 327 397997Ssaidi@eecs.umich.edu#define pt8 328 407997Ssaidi@eecs.umich.edu#define pt9 329 417997Ssaidi@eecs.umich.edu#define pt10 330 427997Ssaidi@eecs.umich.edu#define pt11 331 437997Ssaidi@eecs.umich.edu#define pt12 332 447997Ssaidi@eecs.umich.edu#define pt13 333 457997Ssaidi@eecs.umich.edu#define pt14 334 467997Ssaidi@eecs.umich.edu#define pt15 335 477997Ssaidi@eecs.umich.edu#define pt16 336 487997Ssaidi@eecs.umich.edu#define pt17 337 497997Ssaidi@eecs.umich.edu#define pt18 338 507997Ssaidi@eecs.umich.edu#define pt19 339 517997Ssaidi@eecs.umich.edu#define pt20 340 527997Ssaidi@eecs.umich.edu#define pt21 341 537997Ssaidi@eecs.umich.edu#define pt22 342 547997Ssaidi@eecs.umich.edu#define pt23 343 557997Ssaidi@eecs.umich.edu#define cbox_ipr_offset 16777200 567997Ssaidi@eecs.umich.edu#define sc_ctl 168 577997Ssaidi@eecs.umich.edu#define sc_stat 232 587997Ssaidi@eecs.umich.edu#define sc_addr 392 597997Ssaidi@eecs.umich.edu#define sc_addr_nm 392 607997Ssaidi@eecs.umich.edu#define sc_addr_fhm 392 617997Ssaidi@eecs.umich.edu#define bc_ctl 296 627997Ssaidi@eecs.umich.edu#define bc_config 456 637997Ssaidi@eecs.umich.edu#define ei_stat 360 647997Ssaidi@eecs.umich.edu#define ei_addr 328 657997Ssaidi@eecs.umich.edu#define fill_syn 104 667997Ssaidi@eecs.umich.edu#define bc_tag_addr 264 677997Ssaidi@eecs.umich.edu#define ld_lock 488 687997Ssaidi@eecs.umich.edu#define aster 266 697997Ssaidi@eecs.umich.edu#define astrr 265 707997Ssaidi@eecs.umich.edu#define exc_addr 267 717997Ssaidi@eecs.umich.edu#define exc_sum 268 727997Ssaidi@eecs.umich.edu#define exc_mask 269 737997Ssaidi@eecs.umich.edu#define hwint_clr 277 747997Ssaidi@eecs.umich.edu#define ic_flush_ctl 281 757997Ssaidi@eecs.umich.edu#define icperr_stat 282 767997Ssaidi@eecs.umich.edu#define ic_perr_stat 282 777997Ssaidi@eecs.umich.edu#define ic_row_map 283 787997Ssaidi@eecs.umich.edu#define icsr 280 797997Ssaidi@eecs.umich.edu#define ifault_va_form 274 807997Ssaidi@eecs.umich.edu#define intid 273 817997Ssaidi@eecs.umich.edu#define ipl 272 827997Ssaidi@eecs.umich.edu#define isr 256 837997Ssaidi@eecs.umich.edu#define itb_is 263 847997Ssaidi@eecs.umich.edu#define itb_asn 259 857997Ssaidi@eecs.umich.edu#define itb_ia 261 867997Ssaidi@eecs.umich.edu#define itb_iap 262 877997Ssaidi@eecs.umich.edu#define itb_pte 258 887997Ssaidi@eecs.umich.edu#define itb_pte_temp 260 897997Ssaidi@eecs.umich.edu#define itb_tag 257 907997Ssaidi@eecs.umich.edu#define ivptbr 275 917997Ssaidi@eecs.umich.edu#define pal_base 270 927997Ssaidi@eecs.umich.edu#define pmctr 284 937997Ssaidi@eecs.umich.edu// this is not the register ps .. pb #define ps 271 947997Ssaidi@eecs.umich.edu#define sirr 264 957997Ssaidi@eecs.umich.edu#define sl_txmit 278 967997Ssaidi@eecs.umich.edu#define sl_rcv 279 977997Ssaidi@eecs.umich.edu#define alt_mode 524 987997Ssaidi@eecs.umich.edu#define cc 525 997997Ssaidi@eecs.umich.edu#define cc_ctl 526 1007997Ssaidi@eecs.umich.edu#define dc_flush 528 1017997Ssaidi@eecs.umich.edu#define dcperr_stat 530 1027997Ssaidi@eecs.umich.edu#define dc_test_ctl 531 1037997Ssaidi@eecs.umich.edu#define dc_test_tag 532 1047997Ssaidi@eecs.umich.edu#define dc_test_tag_temp 533 1057997Ssaidi@eecs.umich.edu#define dtb_asn 512 1067997Ssaidi@eecs.umich.edu#define dtb_cm 513 1077997Ssaidi@eecs.umich.edu#define dtb_ia 522 1087997Ssaidi@eecs.umich.edu#define dtb_iap 521 1097997Ssaidi@eecs.umich.edu#define dtb_is 523 1107997Ssaidi@eecs.umich.edu#define dtb_pte 515 1117997Ssaidi@eecs.umich.edu#define dtb_pte_temp 516 1127997Ssaidi@eecs.umich.edu#define dtb_tag 514 1137997Ssaidi@eecs.umich.edu#define mcsr 527 1147997Ssaidi@eecs.umich.edu#define dc_mode 534 1157997Ssaidi@eecs.umich.edu#define maf_mode 535 1167997Ssaidi@eecs.umich.edu#define mm_stat 517 1177997Ssaidi@eecs.umich.edu#define mvptbr 520 1187997Ssaidi@eecs.umich.edu#define va 518 1197997Ssaidi@eecs.umich.edu#define va_form 519 1207997Ssaidi@eecs.umich.edu#define ev5_srm__ps 0 1217997Ssaidi@eecs.umich.edu#define ev5_srm__pc 0 1227997Ssaidi@eecs.umich.edu#define ev5_srm__asten 0 1237997Ssaidi@eecs.umich.edu#define ev5_srm__astsr 0 1247997Ssaidi@eecs.umich.edu#define ev5_srm__ipir 0 1257997Ssaidi@eecs.umich.edu#define ev5_srm__ipl 0 1267997Ssaidi@eecs.umich.edu#define ev5_srm__mces 0 1277997Ssaidi@eecs.umich.edu#define ev5_srm__pcbb 0 1287997Ssaidi@eecs.umich.edu#define ev5_srm__prbr 0 1297997Ssaidi@eecs.umich.edu#define ev5_srm__ptbr 0 1307997Ssaidi@eecs.umich.edu#define ev5_srm__scbb 0 1317997Ssaidi@eecs.umich.edu#define ev5_srm__sirr 0 1327997Ssaidi@eecs.umich.edu#define ev5_srm__sisr 0 1337997Ssaidi@eecs.umich.edu#define ev5_srm__tbchk 0 1347997Ssaidi@eecs.umich.edu#define ev5_srm__tb1a 0 1357997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ap 0 1367997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ad 0 1377997Ssaidi@eecs.umich.edu#define ev5_srm__tb1ai 0 1387997Ssaidi@eecs.umich.edu#define ev5_srm__tbis 0 1397997Ssaidi@eecs.umich.edu#define ev5_srm__ksp 0 1407997Ssaidi@eecs.umich.edu#define ev5_srm__esp 0 1417997Ssaidi@eecs.umich.edu#define ev5_srm__ssp 0 1427997Ssaidi@eecs.umich.edu#define ev5_srm__usp 0 1437997Ssaidi@eecs.umich.edu#define ev5_srm__vptb 0 1447997Ssaidi@eecs.umich.edu#define ev5_srm__whami 0 1457997Ssaidi@eecs.umich.edu#define ev5_srm__cc 0 1467997Ssaidi@eecs.umich.edu#define ev5_srm__unq 0 1477997Ssaidi@eecs.umich.edu// processor-specific iprs. 1487997Ssaidi@eecs.umich.edu#define ev5__sc_ctl 168 1497997Ssaidi@eecs.umich.edu#define ev5__sc_stat 232 1507997Ssaidi@eecs.umich.edu#define ev5__sc_addr 392 1517997Ssaidi@eecs.umich.edu#define ev5__bc_ctl 296 1527997Ssaidi@eecs.umich.edu#define ev5__bc_config 456 1537997Ssaidi@eecs.umich.edu#define bc_config_k_size_1mb 1 1547997Ssaidi@eecs.umich.edu#define bc_config_k_size_2mb 2 1557997Ssaidi@eecs.umich.edu#define bc_config_k_size_4mb 3 1567997Ssaidi@eecs.umich.edu#define bc_config_k_size_8mb 4 1577997Ssaidi@eecs.umich.edu#define bc_config_k_size_16mb 5 1587997Ssaidi@eecs.umich.edu#define bc_config_k_size_32mb 6 1597997Ssaidi@eecs.umich.edu#define bc_config_k_size_64mb 7 1607997Ssaidi@eecs.umich.edu#define ev5__ei_stat 360 1617997Ssaidi@eecs.umich.edu#define ev5__ei_addr 328 1627997Ssaidi@eecs.umich.edu#define ev5__fill_syn 104 1637997Ssaidi@eecs.umich.edu#define ev5__bc_tag_addr 264 1647997Ssaidi@eecs.umich.edu#define ev5__aster 266 1657997Ssaidi@eecs.umich.edu#define ev5__astrr 265 1667997Ssaidi@eecs.umich.edu#define ev5__exc_addr 267 1677997Ssaidi@eecs.umich.edu#define exc_addr_v_pa 2 1687997Ssaidi@eecs.umich.edu#define exc_addr_s_pa 62 1697997Ssaidi@eecs.umich.edu#define ev5__exc_sum 268 1707997Ssaidi@eecs.umich.edu#define ev5__exc_mask 269 1717997Ssaidi@eecs.umich.edu#define ev5__hwint_clr 277 1727997Ssaidi@eecs.umich.edu#define ev5__ic_flush_ctl 281 1737997Ssaidi@eecs.umich.edu#define ev5__icperr_stat 282 1747997Ssaidi@eecs.umich.edu#define ev5__ic_perr_stat 282 1757997Ssaidi@eecs.umich.edu#define ev5__ic_row_map 283 1767997Ssaidi@eecs.umich.edu#define ev5__icsr 280 1777997Ssaidi@eecs.umich.edu#define ev5__ifault_va_form 274 1787997Ssaidi@eecs.umich.edu#define ev5__ifault_va_form_nt 274 1797997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_v_vptb 30 1807997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_s_vptb 34 1817997Ssaidi@eecs.umich.edu#define ev5__intid 273 1827997Ssaidi@eecs.umich.edu#define ev5__ipl 272 1837997Ssaidi@eecs.umich.edu#define ev5__itb_is 263 1847997Ssaidi@eecs.umich.edu#define ev5__itb_asn 259 1857997Ssaidi@eecs.umich.edu#define ev5__itb_ia 261 1867997Ssaidi@eecs.umich.edu#define ev5__itb_iap 262 1877997Ssaidi@eecs.umich.edu#define ev5__itb_pte 258 1887997Ssaidi@eecs.umich.edu#define ev5__itb_pte_temp 260 1897997Ssaidi@eecs.umich.edu#define ev5__itb_tag 257 1907997Ssaidi@eecs.umich.edu#define ev5__ivptbr 275 1917997Ssaidi@eecs.umich.edu#define ivptbr_v_vptb 30 1927997Ssaidi@eecs.umich.edu#define ivptbr_s_vptb 34 1937997Ssaidi@eecs.umich.edu#define ev5__pal_base 270 1947997Ssaidi@eecs.umich.edu#define ev5__pmctr 284 1957997Ssaidi@eecs.umich.edu#define ev5__ps 271 1967997Ssaidi@eecs.umich.edu#define ev5__isr 256 1977997Ssaidi@eecs.umich.edu#define ev5__sirr 264 1987997Ssaidi@eecs.umich.edu#define ev5__sl_txmit 278 1997997Ssaidi@eecs.umich.edu#define ev5__sl_rcv 279 2007997Ssaidi@eecs.umich.edu#define ev5__alt_mode 524 2017997Ssaidi@eecs.umich.edu#define ev5__cc 525 2027997Ssaidi@eecs.umich.edu#define ev5__cc_ctl 526 2037997Ssaidi@eecs.umich.edu#define ev5__dc_flush 528 2047997Ssaidi@eecs.umich.edu#define ev5__dcperr_stat 530 2057997Ssaidi@eecs.umich.edu#define ev5__dc_test_ctl 531 2067997Ssaidi@eecs.umich.edu#define ev5__dc_test_tag 532 2077997Ssaidi@eecs.umich.edu#define ev5__dc_test_tag_temp 533 2087997Ssaidi@eecs.umich.edu#define ev5__dtb_asn 512 2097997Ssaidi@eecs.umich.edu#define ev5__dtb_cm 513 2107997Ssaidi@eecs.umich.edu#define ev5__dtb_ia 522 2117997Ssaidi@eecs.umich.edu#define ev5__dtb_iap 521 2127997Ssaidi@eecs.umich.edu#define ev5__dtb_is 523 2137997Ssaidi@eecs.umich.edu#define ev5__dtb_pte 515 2147997Ssaidi@eecs.umich.edu#define ev5__dtb_pte_temp 516 2157997Ssaidi@eecs.umich.edu#define ev5__dtb_tag 514 2167997Ssaidi@eecs.umich.edu#define ev5__mcsr 527 2177997Ssaidi@eecs.umich.edu#define ev5__dc_mode 534 2187997Ssaidi@eecs.umich.edu#define ev5__maf_mode 535 2197997Ssaidi@eecs.umich.edu#define ev5__mm_stat 517 2207997Ssaidi@eecs.umich.edu#define ev5__mvptbr 520 2217997Ssaidi@eecs.umich.edu#define ev5__va 518 2227997Ssaidi@eecs.umich.edu#define ev5__va_form 519 2237997Ssaidi@eecs.umich.edu#define ev5__va_form_nt 519 2247997Ssaidi@eecs.umich.edu#define va_form_nt_s_va 19 2257997Ssaidi@eecs.umich.edu#define va_form_nt_v_vptb 30 2267997Ssaidi@eecs.umich.edu#define va_form_nt_s_vptb 34 2277997Ssaidi@eecs.umich.edu#define ev5s_ev5_def 10 2287997Ssaidi@eecs.umich.edu#define ev5_def 0 2297997Ssaidi@eecs.umich.edu// cbox registers. 2307997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_fhit 0 2317997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_flush 1 2327997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_tag_stat 6 2337997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_tag_stat 2 2347997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_fb_dp 4 2357997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_fb_dp 8 2367997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_blk_size 12 2377997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_set_en 3 2387997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_set_en 13 2397997Ssaidi@eecs.umich.edu#define sc_ctl_s_sc_soft_repair 3 2407997Ssaidi@eecs.umich.edu#define sc_ctl_v_sc_soft_repair 16 2417997Ssaidi@eecs.umich.edu#define sc_stat_s_sc_tperr 3 2427997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_tperr 0 2437997Ssaidi@eecs.umich.edu#define sc_stat_s_sc_dperr 8 2447997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_dperr 3 2457997Ssaidi@eecs.umich.edu#define sc_stat_s_cbox_cmd 5 2467997Ssaidi@eecs.umich.edu#define sc_stat_v_cbox_cmd 11 2477997Ssaidi@eecs.umich.edu#define sc_stat_v_sc_scnd_err 16 2487997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_sc_tag_parity 4 2497997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_stat_sb0 3 2507997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_stat_sb0 5 2517997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_stat_sb1 3 2527997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_stat_sb1 8 2537997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_ow_mod0 2 2547997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_ow_mod0 11 2557997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_ow_mod1 2 2567997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_ow_mod1 13 2577997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_lo 17 2587997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_lo 15 2597997Ssaidi@eecs.umich.edu#define sc_addr_fhm_s_tag_hi 7 2607997Ssaidi@eecs.umich.edu#define sc_addr_fhm_v_tag_hi 32 2617997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_enabled 0 2627997Ssaidi@eecs.umich.edu#define bc_ctl_v_alloc_cyc 1 2637997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_opt_cmd 2 2647997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_opt_cmd_mb 3 2657997Ssaidi@eecs.umich.edu#define bc_ctl_v_corr_fill_dat 4 2667997Ssaidi@eecs.umich.edu#define bc_ctl_v_vtm_first 5 2677997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_ecc_or_parity 6 2687997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_fhit 7 2697997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_tag_stat 5 2707997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_tag_stat 8 2717997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_bad_dat 2 2727997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_bad_dat 13 2737997Ssaidi@eecs.umich.edu#define bc_ctl_v_ei_dis_err 15 2747997Ssaidi@eecs.umich.edu#define bc_ctl_v_tl_pipe_latch 16 2757997Ssaidi@eecs.umich.edu#define bc_ctl_s_bc_wave_pipe 2 2767997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_wave_pipe 17 2777997Ssaidi@eecs.umich.edu#define bc_ctl_s_pm_mux_sel 6 2787997Ssaidi@eecs.umich.edu#define bc_ctl_v_pm_mux_sel 19 2797997Ssaidi@eecs.umich.edu#define bc_ctl_v_dbg_mux_sel 25 2807997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_baf_byp 26 2817997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_sc_vic_buf 27 2827997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_sys_addr_par 28 2837997Ssaidi@eecs.umich.edu#define bc_ctl_v_read_dirty_cln_shr 29 2847997Ssaidi@eecs.umich.edu#define bc_ctl_v_write_read_bubble 30 2857997Ssaidi@eecs.umich.edu#define bc_ctl_v_bc_wave_pipe_2 31 2867997Ssaidi@eecs.umich.edu#define bc_ctl_v_auto_dack 32 2877997Ssaidi@eecs.umich.edu#define bc_ctl_v_dis_byte_word 33 2887997Ssaidi@eecs.umich.edu#define bc_ctl_v_stclk_delay 34 2897997Ssaidi@eecs.umich.edu#define bc_ctl_v_write_under_miss 35 2907997Ssaidi@eecs.umich.edu#define bc_config_s_bc_size 3 2917997Ssaidi@eecs.umich.edu#define bc_config_v_bc_size 0 2927997Ssaidi@eecs.umich.edu#define bc_config_s_bc_rd_spd 4 2937997Ssaidi@eecs.umich.edu#define bc_config_v_bc_rd_spd 4 2947997Ssaidi@eecs.umich.edu#define bc_config_s_bc_wr_spd 4 2957997Ssaidi@eecs.umich.edu#define bc_config_v_bc_wr_spd 8 2967997Ssaidi@eecs.umich.edu#define bc_config_s_bc_rd_wr_spc 3 2977997Ssaidi@eecs.umich.edu#define bc_config_v_bc_rd_wr_spc 12 2987997Ssaidi@eecs.umich.edu#define bc_config_s_fill_we_offset 3 2997997Ssaidi@eecs.umich.edu#define bc_config_v_fill_we_offset 16 3007997Ssaidi@eecs.umich.edu#define bc_config_s_bc_we_ctl 9 3017997Ssaidi@eecs.umich.edu#define bc_config_v_bc_we_ctl 20 3027997Ssaidi@eecs.umich.edu// cbox registers, continued 3037997Ssaidi@eecs.umich.edu#define ei_stat_s_sys_id 4 3047997Ssaidi@eecs.umich.edu#define ei_stat_v_sys_id 24 3057997Ssaidi@eecs.umich.edu#define ei_stat_v_bc_tperr 28 3067997Ssaidi@eecs.umich.edu#define ei_stat_v_bc_tc_perr 29 3077997Ssaidi@eecs.umich.edu#define ei_stat_v_ei_es 30 3087997Ssaidi@eecs.umich.edu#define ei_stat_v_cor_ecc_err 31 3097997Ssaidi@eecs.umich.edu#define ei_stat_v_unc_ecc_err 32 3107997Ssaidi@eecs.umich.edu#define ei_stat_v_ei_par_err 33 3117997Ssaidi@eecs.umich.edu#define ei_stat_v_fil_ird 34 3127997Ssaidi@eecs.umich.edu#define ei_stat_v_seo_hrd_err 35 3137997Ssaidi@eecs.umich.edu// 3147997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_hit 12 3157997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_p 13 3167997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_d 14 3177997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_s 15 3187997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tagctl_v 16 3197997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_tag_p 17 3207997Ssaidi@eecs.umich.edu#define bc_tag_addr_s_bc_tag 19 3217997Ssaidi@eecs.umich.edu#define bc_tag_addr_v_bc_tag 20 3227997Ssaidi@eecs.umich.edu// ibox and icache registers. 3237997Ssaidi@eecs.umich.edu#define aster_v_kar 0 3247997Ssaidi@eecs.umich.edu#define aster_v_ear 1 3257997Ssaidi@eecs.umich.edu#define aster_v_sar 2 3267997Ssaidi@eecs.umich.edu#define aster_v_uar 3 3277997Ssaidi@eecs.umich.edu#define astrr_v_kar 0 3287997Ssaidi@eecs.umich.edu#define astrr_v_ear 1 3297997Ssaidi@eecs.umich.edu#define astrr_v_sar 2 3307997Ssaidi@eecs.umich.edu#define astrr_v_uar 3 3317997Ssaidi@eecs.umich.edu#define exc_addr_v_pal 0 3327997Ssaidi@eecs.umich.edu#define exc_sum_v_swc 10 3337997Ssaidi@eecs.umich.edu#define exc_sum_v_inv 11 3347997Ssaidi@eecs.umich.edu#define exc_sum_v_dze 12 3357997Ssaidi@eecs.umich.edu#define exc_sum_v_fov 13 3367997Ssaidi@eecs.umich.edu#define exc_sum_v_unf 14 3377997Ssaidi@eecs.umich.edu#define exc_sum_v_ine 15 3387997Ssaidi@eecs.umich.edu#define exc_sum_v_iov 16 3397997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc0c 27 3407997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc1c 28 3417997Ssaidi@eecs.umich.edu#define hwint_clr_v_pc2c 29 3427997Ssaidi@eecs.umich.edu#define hwint_clr_v_crdc 32 3437997Ssaidi@eecs.umich.edu#define hwint_clr_v_slc 33 3447997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 3457997Ssaidi@eecs.umich.edu#define icperr_stat_v_dpe 11 3467997Ssaidi@eecs.umich.edu#define icperr_stat_v_tpe 12 3477997Ssaidi@eecs.umich.edu#define icperr_stat_v_tmr 13 3487997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_dpe 11 3497997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_tpe 12 3507997Ssaidi@eecs.umich.edu#define ic_perr_stat_v_tmr 13 3517997Ssaidi@eecs.umich.edu#define icsr_v_pma 8 3527997Ssaidi@eecs.umich.edu#define icsr_v_pmp 9 3537997Ssaidi@eecs.umich.edu#define icsr_v_byt 17 3547997Ssaidi@eecs.umich.edu#define icsr_v_fmp 18 3557997Ssaidi@eecs.umich.edu#define icsr_v_im0 20 3567997Ssaidi@eecs.umich.edu#define icsr_v_im1 21 3577997Ssaidi@eecs.umich.edu#define icsr_v_im2 22 3587997Ssaidi@eecs.umich.edu#define icsr_v_im3 23 3597997Ssaidi@eecs.umich.edu#define icsr_v_tmm 24 3607997Ssaidi@eecs.umich.edu#define icsr_v_tmd 25 3617997Ssaidi@eecs.umich.edu#define icsr_v_fpe 26 3627997Ssaidi@eecs.umich.edu#define icsr_v_hwe 27 3637997Ssaidi@eecs.umich.edu#define icsr_s_spe 2 3647997Ssaidi@eecs.umich.edu#define icsr_v_spe 28 3657997Ssaidi@eecs.umich.edu#define icsr_v_sde 30 3667997Ssaidi@eecs.umich.edu#define icsr_v_crde 32 3677997Ssaidi@eecs.umich.edu#define icsr_v_sle 33 3687997Ssaidi@eecs.umich.edu#define icsr_v_fms 34 3697997Ssaidi@eecs.umich.edu#define icsr_v_fbt 35 3707997Ssaidi@eecs.umich.edu#define icsr_v_fbd 36 3717997Ssaidi@eecs.umich.edu#define icsr_v_dbs 37 3727997Ssaidi@eecs.umich.edu#define icsr_v_ista 38 3737997Ssaidi@eecs.umich.edu#define icsr_v_tst 39 3747997Ssaidi@eecs.umich.edu#define ifault_va_form_s_va 30 3757997Ssaidi@eecs.umich.edu#define ifault_va_form_v_va 3 3767997Ssaidi@eecs.umich.edu#define ifault_va_form_s_vptb 31 3777997Ssaidi@eecs.umich.edu#define ifault_va_form_v_vptb 33 3787997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_s_va 19 3797997Ssaidi@eecs.umich.edu#define ifault_va_form_nt_v_va 3 3807997Ssaidi@eecs.umich.edu#define intid_s_intid 5 3817997Ssaidi@eecs.umich.edu#define intid_v_intid 0 3827997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 3837997Ssaidi@eecs.umich.edu#define ipl_s_ipl 5 3847997Ssaidi@eecs.umich.edu#define ipl_v_ipl 0 3857997Ssaidi@eecs.umich.edu#define itb_is_s_va 30 3867997Ssaidi@eecs.umich.edu#define itb_is_v_va 13 3877997Ssaidi@eecs.umich.edu#define itb_asn_s_asn 7 3887997Ssaidi@eecs.umich.edu#define itb_asn_v_asn 4 3897997Ssaidi@eecs.umich.edu#define itb_pte_v_asm 4 3907997Ssaidi@eecs.umich.edu#define itb_pte_s_gh 2 3917997Ssaidi@eecs.umich.edu#define itb_pte_v_gh 5 3927997Ssaidi@eecs.umich.edu#define itb_pte_v_kre 8 3937997Ssaidi@eecs.umich.edu#define itb_pte_v_ere 9 3947997Ssaidi@eecs.umich.edu#define itb_pte_v_sre 10 3957997Ssaidi@eecs.umich.edu#define itb_pte_v_ure 11 3967997Ssaidi@eecs.umich.edu#define itb_pte_s_pfn 27 3977997Ssaidi@eecs.umich.edu#define itb_pte_v_pfn 32 3987997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_asm 13 3997997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_kre 18 4007997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_ere 19 4017997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_sre 20 4027997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_ure 21 4037997Ssaidi@eecs.umich.edu#define itb_pte_temp_s_gh 3 4047997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_gh 29 4057997Ssaidi@eecs.umich.edu#define itb_pte_temp_s_pfn 27 4067997Ssaidi@eecs.umich.edu#define itb_pte_temp_v_pfn 32 4077997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 4087997Ssaidi@eecs.umich.edu#define itb_tag_s_va 30 4097997Ssaidi@eecs.umich.edu#define itb_tag_v_va 13 4107997Ssaidi@eecs.umich.edu#define pal_base_s_pal_base 26 4117997Ssaidi@eecs.umich.edu#define pal_base_v_pal_base 14 4127997Ssaidi@eecs.umich.edu#define pmctr_s_sel2 4 4137997Ssaidi@eecs.umich.edu#define pmctr_v_sel2 0 4147997Ssaidi@eecs.umich.edu#define pmctr_s_sel1 4 4157997Ssaidi@eecs.umich.edu#define pmctr_v_sel1 4 4167997Ssaidi@eecs.umich.edu#define pmctr_v_killk 8 4177997Ssaidi@eecs.umich.edu#define pmctr_v_killp 9 4187997Ssaidi@eecs.umich.edu#define pmctr_s_ctl2 2 4197997Ssaidi@eecs.umich.edu#define pmctr_v_ctl2 10 4207997Ssaidi@eecs.umich.edu#define pmctr_s_ctl1 2 4217997Ssaidi@eecs.umich.edu#define pmctr_v_ctl1 12 4227997Ssaidi@eecs.umich.edu#define pmctr_s_ctl0 2 4237997Ssaidi@eecs.umich.edu#define pmctr_v_ctl0 14 4247997Ssaidi@eecs.umich.edu#define pmctr_s_ctr2 14 4257997Ssaidi@eecs.umich.edu#define pmctr_v_ctr2 16 4267997Ssaidi@eecs.umich.edu#define pmctr_v_killu 30 4277997Ssaidi@eecs.umich.edu#define pmctr_v_sel0 31 4287997Ssaidi@eecs.umich.edu#define pmctr_s_ctr1 16 4297997Ssaidi@eecs.umich.edu#define pmctr_v_ctr1 32 4307997Ssaidi@eecs.umich.edu#define pmctr_s_ctr0 16 4317997Ssaidi@eecs.umich.edu#define pmctr_v_ctr0 48 4327997Ssaidi@eecs.umich.edu#define ps_v_cm0 3 4337997Ssaidi@eecs.umich.edu#define ps_v_cm1 4 4347997Ssaidi@eecs.umich.edu#define isr_s_astrr 4 4357997Ssaidi@eecs.umich.edu#define isr_v_astrr 0 4367997Ssaidi@eecs.umich.edu#define isr_s_sisr 15 4377997Ssaidi@eecs.umich.edu#define isr_v_sisr 4 4387997Ssaidi@eecs.umich.edu#define isr_v_atr 19 4397997Ssaidi@eecs.umich.edu#define isr_v_i20 20 4407997Ssaidi@eecs.umich.edu#define isr_v_i21 21 4417997Ssaidi@eecs.umich.edu#define isr_v_i22 22 4427997Ssaidi@eecs.umich.edu#define isr_v_i23 23 4437997Ssaidi@eecs.umich.edu#define isr_v_pc0 27 4447997Ssaidi@eecs.umich.edu#define isr_v_pc1 28 4457997Ssaidi@eecs.umich.edu#define isr_v_pc2 29 4467997Ssaidi@eecs.umich.edu#define isr_v_pfl 30 4477997Ssaidi@eecs.umich.edu#define isr_v_mck 31 4487997Ssaidi@eecs.umich.edu#define isr_v_crd 32 4497997Ssaidi@eecs.umich.edu#define isr_v_sli 33 4507997Ssaidi@eecs.umich.edu#define isr_v_hlt 34 4517997Ssaidi@eecs.umich.edu#define sirr_s_sirr 15 4527997Ssaidi@eecs.umich.edu#define sirr_v_sirr 4 4537997Ssaidi@eecs.umich.edu// ibox and icache registers, continued 4547997Ssaidi@eecs.umich.edu#define sl_txmit_v_tmt 7 4557997Ssaidi@eecs.umich.edu#define sl_rcv_v_rcv 6 4567997Ssaidi@eecs.umich.edu// mbox and dcache registers. 4577997Ssaidi@eecs.umich.edu#define alt_mode_v_am0 3 4587997Ssaidi@eecs.umich.edu#define alt_mode_v_am1 4 4597997Ssaidi@eecs.umich.edu#define cc_ctl_v_cc_ena 32 4607997Ssaidi@eecs.umich.edu#define dcperr_stat_v_seo 0 4617997Ssaidi@eecs.umich.edu#define dcperr_stat_v_lock 1 4627997Ssaidi@eecs.umich.edu#define dcperr_stat_v_dp0 2 4637997Ssaidi@eecs.umich.edu#define dcperr_stat_v_dp1 3 4647997Ssaidi@eecs.umich.edu#define dcperr_stat_v_tp0 4 4657997Ssaidi@eecs.umich.edu#define dcperr_stat_v_tp1 5 4667997Ssaidi@eecs.umich.edu// the following two registers are used exclusively for test and diagnostics. 4677997Ssaidi@eecs.umich.edu// they should not be referenced in normal operation. 4687997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_bank0 0 4697997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_bank1 1 4707997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_0 2 4717997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_index 10 4727997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_index 3 4737997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_fill_1 19 4747997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_1 13 4757997Ssaidi@eecs.umich.edu#define dc_test_ctl_s_fill_2 32 4767997Ssaidi@eecs.umich.edu#define dc_test_ctl_v_fill_2 32 4777997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 4787997Ssaidi@eecs.umich.edu#define dc_test_tag_v_tag_par 2 4797997Ssaidi@eecs.umich.edu#define dc_test_tag_v_ow0 11 4807997Ssaidi@eecs.umich.edu#define dc_test_tag_v_ow1 12 4817997Ssaidi@eecs.umich.edu#define dc_test_tag_s_tag 26 4827997Ssaidi@eecs.umich.edu#define dc_test_tag_v_tag 13 4837997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_tag_par 2 4847997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d0p0 3 4857997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d0p1 4 4867997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d1p0 5 4877997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_d1p1 6 4887997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_ow0 11 4897997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_ow1 12 4907997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_s_tag 26 4917997Ssaidi@eecs.umich.edu#define dc_test_tag_temp_v_tag 13 4927997Ssaidi@eecs.umich.edu#define dtb_asn_s_asn 7 4937997Ssaidi@eecs.umich.edu#define dtb_asn_v_asn 57 4947997Ssaidi@eecs.umich.edu#define dtb_cm_v_cm0 3 4957997Ssaidi@eecs.umich.edu#define dtb_cm_v_cm1 4 4967997Ssaidi@eecs.umich.edu#define dtbis_s_va0 30 4977997Ssaidi@eecs.umich.edu#define dtbis_v_va0 13 4987997Ssaidi@eecs.umich.edu#define dtb_pte_v_for 1 4997997Ssaidi@eecs.umich.edu#define dtb_pte_v_fow 2 5007997Ssaidi@eecs.umich.edu#define dtb_pte_v_asm 4 5017997Ssaidi@eecs.umich.edu#define dtb_pte_s_gh 2 5027997Ssaidi@eecs.umich.edu#define dtb_pte_v_gh 5 5037997Ssaidi@eecs.umich.edu#define dtb_pte_v_kre 8 5047997Ssaidi@eecs.umich.edu#define dtb_pte_v_ere 9 5057997Ssaidi@eecs.umich.edu#define dtb_pte_v_sre 10 5067997Ssaidi@eecs.umich.edu#define dtb_pte_v_ure 11 5077997Ssaidi@eecs.umich.edu#define dtb_pte_v_kwe 12 5087997Ssaidi@eecs.umich.edu#define dtb_pte_v_ewe 13 5097997Ssaidi@eecs.umich.edu#define dtb_pte_v_swe 14 5107997Ssaidi@eecs.umich.edu#define dtb_pte_v_uwe 15 5117997Ssaidi@eecs.umich.edu#define dtb_pte_s_pfn 27 5127997Ssaidi@eecs.umich.edu#define dtb_pte_v_pfn 32 5137997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 5147997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_for 0 5157997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_fow 1 5167997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_kre 2 5177997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ere 3 5187997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_sre 4 5197997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ure 5 5207997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_kwe 6 5217997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_ewe 7 5227997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_swe 8 5237997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_uwe 9 5247997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_asm 10 5257997Ssaidi@eecs.umich.edu#define dtb_pte_temp_s_fill_0 2 5267997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_fill_0 11 5277997Ssaidi@eecs.umich.edu#define dtb_pte_temp_s_pfn 27 5287997Ssaidi@eecs.umich.edu#define dtb_pte_temp_v_pfn 13 5297997Ssaidi@eecs.umich.edu#define dtb_tag_s_va 30 5307997Ssaidi@eecs.umich.edu#define dtb_tag_v_va 13 5317997Ssaidi@eecs.umich.edu// most mcsr bits are used for testability and diagnostics only. 5327997Ssaidi@eecs.umich.edu// for normal operation, they will be supported in the following configuration: 5337997Ssaidi@eecs.umich.edu// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, 5347997Ssaidi@eecs.umich.edu// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 5357997Ssaidi@eecs.umich.edu#define mcsr_v_big_endian 0 5367997Ssaidi@eecs.umich.edu#define mcsr_v_sp0 1 5377997Ssaidi@eecs.umich.edu#define mcsr_v_sp1 2 5387997Ssaidi@eecs.umich.edu#define mcsr_v_mbox_sel 3 5397997Ssaidi@eecs.umich.edu#define mcsr_v_e_big_endian 4 5407997Ssaidi@eecs.umich.edu#define mcsr_v_dbg_packet_sel 5 5417997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_ena 0 5427997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_fhit 1 5437997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_bad_parity 2 5447997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_perr_dis 3 5457997Ssaidi@eecs.umich.edu#define dc_mode_v_dc_doa 4 5467997Ssaidi@eecs.umich.edu#define maf_mode_v_maf_nomerge 0 5477997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_flush_always 1 5487997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_nomerge 2 5497997Ssaidi@eecs.umich.edu#define maf_mode_v_io_nomerge 3 5507997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_cnt_disable 4 5517997Ssaidi@eecs.umich.edu#define maf_mode_v_maf_arb_disable 5 5527997Ssaidi@eecs.umich.edu#define maf_mode_v_dread_pending 6 5537997Ssaidi@eecs.umich.edu#define maf_mode_v_wb_pending 7 5547997Ssaidi@eecs.umich.edu// mbox and dcache registers, continued. 5557997Ssaidi@eecs.umich.edu#define mm_stat_v_wr 0 5567997Ssaidi@eecs.umich.edu#define mm_stat_v_acv 1 5577997Ssaidi@eecs.umich.edu#define mm_stat_v_for 2 5587997Ssaidi@eecs.umich.edu#define mm_stat_v_fow 3 5597997Ssaidi@eecs.umich.edu#define mm_stat_v_dtb_miss 4 5607997Ssaidi@eecs.umich.edu#define mm_stat_v_bad_va 5 5617997Ssaidi@eecs.umich.edu#define mm_stat_s_ra 5 5627997Ssaidi@eecs.umich.edu#define mm_stat_v_ra 6 5637997Ssaidi@eecs.umich.edu#define mm_stat_s_opcode 6 5647997Ssaidi@eecs.umich.edu#define mm_stat_v_opcode 11 5657997Ssaidi@eecs.umich.edu#define mvptbr_s_vptb 31 5667997Ssaidi@eecs.umich.edu#define mvptbr_v_vptb 33 5677997Ssaidi@eecs.umich.edu#define va_form_s_va 30 5687997Ssaidi@eecs.umich.edu#define va_form_v_va 3 5697997Ssaidi@eecs.umich.edu#define va_form_s_vptb 31 5707997Ssaidi@eecs.umich.edu#define va_form_v_vptb 33 5717997Ssaidi@eecs.umich.edu#define va_form_nt_s_va 19 5727997Ssaidi@eecs.umich.edu#define va_form_nt_v_va 3 5737997Ssaidi@eecs.umich.edu//.endm 5747997Ssaidi@eecs.umich.edu 5757997Ssaidi@eecs.umich.edu#endif 576