ev5_defs.h revision 7997
1#ifndef EV5_DEFS_INCLUDED 2#define EV5_DEFS_INCLUDED 1 3 4// adapted from the version emailed to lance..pb Nov/95 5 6 7// ******************************************************************************************************************************** 8// Created 25-JUL-1995 14:21:23 by VAX SDL V3.2-12 Source: 21-JUL-1995 11:03:08 EV5$:[EV5.DVT.SUP]EV5_DEFS.SDL;24 9// ******************************************************************************************************************************** 10 11// .MACRO $EV5DEF,..EQU=<=>,..COL=<:> 12// EV5$K_REVISION'..equ'34 13// In the definitions below, registers are annotated with one of the following 14// symbols: 15// 16// RW - The register may be read and written 17// RO - The register may only be read 18// WO - The register may only be written 19// 20// For RO and WO registers, all bits and fields within the register are also 21// read-only or write-only. For RW registers, each bit or field within 22// the register is annotated with one of the following: 23// 24// RW - The bit/field may be read and written 25// RO - The bit/field may be read; writes are ignored 26// WO - The bit/field may be written; reads return an UNPREDICTABLE result. 27// WZ - The bit/field may be written; reads return a 0 28// WC - The bit/field may be read; writes cause state to clear 29// RC - The bit/field may be read, which also causes state to clear; writes are ignored 30// Architecturally-defined (SRM) registers for EVMS 31#define pt0 320 32#define pt1 321 33#define pt2 322 34#define pt3 323 35#define pt4 324 36#define pt5 325 37#define pt6 326 38#define pt7 327 39#define pt8 328 40#define pt9 329 41#define pt10 330 42#define pt11 331 43#define pt12 332 44#define pt13 333 45#define pt14 334 46#define pt15 335 47#define pt16 336 48#define pt17 337 49#define pt18 338 50#define pt19 339 51#define pt20 340 52#define pt21 341 53#define pt22 342 54#define pt23 343 55#define cbox_ipr_offset 16777200 56#define sc_ctl 168 57#define sc_stat 232 58#define sc_addr 392 59#define sc_addr_nm 392 60#define sc_addr_fhm 392 61#define bc_ctl 296 62#define bc_config 456 63#define ei_stat 360 64#define ei_addr 328 65#define fill_syn 104 66#define bc_tag_addr 264 67#define ld_lock 488 68#define aster 266 69#define astrr 265 70#define exc_addr 267 71#define exc_sum 268 72#define exc_mask 269 73#define hwint_clr 277 74#define ic_flush_ctl 281 75#define icperr_stat 282 76#define ic_perr_stat 282 77#define ic_row_map 283 78#define icsr 280 79#define ifault_va_form 274 80#define intid 273 81#define ipl 272 82#define isr 256 83#define itb_is 263 84#define itb_asn 259 85#define itb_ia 261 86#define itb_iap 262 87#define itb_pte 258 88#define itb_pte_temp 260 89#define itb_tag 257 90#define ivptbr 275 91#define pal_base 270 92#define pmctr 284 93// this is not the register ps .. pb #define ps 271 94#define sirr 264 95#define sl_txmit 278 96#define sl_rcv 279 97#define alt_mode 524 98#define cc 525 99#define cc_ctl 526 100#define dc_flush 528 101#define dcperr_stat 530 102#define dc_test_ctl 531 103#define dc_test_tag 532 104#define dc_test_tag_temp 533 105#define dtb_asn 512 106#define dtb_cm 513 107#define dtb_ia 522 108#define dtb_iap 521 109#define dtb_is 523 110#define dtb_pte 515 111#define dtb_pte_temp 516 112#define dtb_tag 514 113#define mcsr 527 114#define dc_mode 534 115#define maf_mode 535 116#define mm_stat 517 117#define mvptbr 520 118#define va 518 119#define va_form 519 120#define ev5_srm__ps 0 121#define ev5_srm__pc 0 122#define ev5_srm__asten 0 123#define ev5_srm__astsr 0 124#define ev5_srm__ipir 0 125#define ev5_srm__ipl 0 126#define ev5_srm__mces 0 127#define ev5_srm__pcbb 0 128#define ev5_srm__prbr 0 129#define ev5_srm__ptbr 0 130#define ev5_srm__scbb 0 131#define ev5_srm__sirr 0 132#define ev5_srm__sisr 0 133#define ev5_srm__tbchk 0 134#define ev5_srm__tb1a 0 135#define ev5_srm__tb1ap 0 136#define ev5_srm__tb1ad 0 137#define ev5_srm__tb1ai 0 138#define ev5_srm__tbis 0 139#define ev5_srm__ksp 0 140#define ev5_srm__esp 0 141#define ev5_srm__ssp 0 142#define ev5_srm__usp 0 143#define ev5_srm__vptb 0 144#define ev5_srm__whami 0 145#define ev5_srm__cc 0 146#define ev5_srm__unq 0 147// processor-specific iprs. 148#define ev5__sc_ctl 168 149#define ev5__sc_stat 232 150#define ev5__sc_addr 392 151#define ev5__bc_ctl 296 152#define ev5__bc_config 456 153#define bc_config_k_size_1mb 1 154#define bc_config_k_size_2mb 2 155#define bc_config_k_size_4mb 3 156#define bc_config_k_size_8mb 4 157#define bc_config_k_size_16mb 5 158#define bc_config_k_size_32mb 6 159#define bc_config_k_size_64mb 7 160#define ev5__ei_stat 360 161#define ev5__ei_addr 328 162#define ev5__fill_syn 104 163#define ev5__bc_tag_addr 264 164#define ev5__aster 266 165#define ev5__astrr 265 166#define ev5__exc_addr 267 167#define exc_addr_v_pa 2 168#define exc_addr_s_pa 62 169#define ev5__exc_sum 268 170#define ev5__exc_mask 269 171#define ev5__hwint_clr 277 172#define ev5__ic_flush_ctl 281 173#define ev5__icperr_stat 282 174#define ev5__ic_perr_stat 282 175#define ev5__ic_row_map 283 176#define ev5__icsr 280 177#define ev5__ifault_va_form 274 178#define ev5__ifault_va_form_nt 274 179#define ifault_va_form_nt_v_vptb 30 180#define ifault_va_form_nt_s_vptb 34 181#define ev5__intid 273 182#define ev5__ipl 272 183#define ev5__itb_is 263 184#define ev5__itb_asn 259 185#define ev5__itb_ia 261 186#define ev5__itb_iap 262 187#define ev5__itb_pte 258 188#define ev5__itb_pte_temp 260 189#define ev5__itb_tag 257 190#define ev5__ivptbr 275 191#define ivptbr_v_vptb 30 192#define ivptbr_s_vptb 34 193#define ev5__pal_base 270 194#define ev5__pmctr 284 195#define ev5__ps 271 196#define ev5__isr 256 197#define ev5__sirr 264 198#define ev5__sl_txmit 278 199#define ev5__sl_rcv 279 200#define ev5__alt_mode 524 201#define ev5__cc 525 202#define ev5__cc_ctl 526 203#define ev5__dc_flush 528 204#define ev5__dcperr_stat 530 205#define ev5__dc_test_ctl 531 206#define ev5__dc_test_tag 532 207#define ev5__dc_test_tag_temp 533 208#define ev5__dtb_asn 512 209#define ev5__dtb_cm 513 210#define ev5__dtb_ia 522 211#define ev5__dtb_iap 521 212#define ev5__dtb_is 523 213#define ev5__dtb_pte 515 214#define ev5__dtb_pte_temp 516 215#define ev5__dtb_tag 514 216#define ev5__mcsr 527 217#define ev5__dc_mode 534 218#define ev5__maf_mode 535 219#define ev5__mm_stat 517 220#define ev5__mvptbr 520 221#define ev5__va 518 222#define ev5__va_form 519 223#define ev5__va_form_nt 519 224#define va_form_nt_s_va 19 225#define va_form_nt_v_vptb 30 226#define va_form_nt_s_vptb 34 227#define ev5s_ev5_def 10 228#define ev5_def 0 229// cbox registers. 230#define sc_ctl_v_sc_fhit 0 231#define sc_ctl_v_sc_flush 1 232#define sc_ctl_s_sc_tag_stat 6 233#define sc_ctl_v_sc_tag_stat 2 234#define sc_ctl_s_sc_fb_dp 4 235#define sc_ctl_v_sc_fb_dp 8 236#define sc_ctl_v_sc_blk_size 12 237#define sc_ctl_s_sc_set_en 3 238#define sc_ctl_v_sc_set_en 13 239#define sc_ctl_s_sc_soft_repair 3 240#define sc_ctl_v_sc_soft_repair 16 241#define sc_stat_s_sc_tperr 3 242#define sc_stat_v_sc_tperr 0 243#define sc_stat_s_sc_dperr 8 244#define sc_stat_v_sc_dperr 3 245#define sc_stat_s_cbox_cmd 5 246#define sc_stat_v_cbox_cmd 11 247#define sc_stat_v_sc_scnd_err 16 248#define sc_addr_fhm_v_sc_tag_parity 4 249#define sc_addr_fhm_s_tag_stat_sb0 3 250#define sc_addr_fhm_v_tag_stat_sb0 5 251#define sc_addr_fhm_s_tag_stat_sb1 3 252#define sc_addr_fhm_v_tag_stat_sb1 8 253#define sc_addr_fhm_s_ow_mod0 2 254#define sc_addr_fhm_v_ow_mod0 11 255#define sc_addr_fhm_s_ow_mod1 2 256#define sc_addr_fhm_v_ow_mod1 13 257#define sc_addr_fhm_s_tag_lo 17 258#define sc_addr_fhm_v_tag_lo 15 259#define sc_addr_fhm_s_tag_hi 7 260#define sc_addr_fhm_v_tag_hi 32 261#define bc_ctl_v_bc_enabled 0 262#define bc_ctl_v_alloc_cyc 1 263#define bc_ctl_v_ei_opt_cmd 2 264#define bc_ctl_v_ei_opt_cmd_mb 3 265#define bc_ctl_v_corr_fill_dat 4 266#define bc_ctl_v_vtm_first 5 267#define bc_ctl_v_ei_ecc_or_parity 6 268#define bc_ctl_v_bc_fhit 7 269#define bc_ctl_s_bc_tag_stat 5 270#define bc_ctl_v_bc_tag_stat 8 271#define bc_ctl_s_bc_bad_dat 2 272#define bc_ctl_v_bc_bad_dat 13 273#define bc_ctl_v_ei_dis_err 15 274#define bc_ctl_v_tl_pipe_latch 16 275#define bc_ctl_s_bc_wave_pipe 2 276#define bc_ctl_v_bc_wave_pipe 17 277#define bc_ctl_s_pm_mux_sel 6 278#define bc_ctl_v_pm_mux_sel 19 279#define bc_ctl_v_dbg_mux_sel 25 280#define bc_ctl_v_dis_baf_byp 26 281#define bc_ctl_v_dis_sc_vic_buf 27 282#define bc_ctl_v_dis_sys_addr_par 28 283#define bc_ctl_v_read_dirty_cln_shr 29 284#define bc_ctl_v_write_read_bubble 30 285#define bc_ctl_v_bc_wave_pipe_2 31 286#define bc_ctl_v_auto_dack 32 287#define bc_ctl_v_dis_byte_word 33 288#define bc_ctl_v_stclk_delay 34 289#define bc_ctl_v_write_under_miss 35 290#define bc_config_s_bc_size 3 291#define bc_config_v_bc_size 0 292#define bc_config_s_bc_rd_spd 4 293#define bc_config_v_bc_rd_spd 4 294#define bc_config_s_bc_wr_spd 4 295#define bc_config_v_bc_wr_spd 8 296#define bc_config_s_bc_rd_wr_spc 3 297#define bc_config_v_bc_rd_wr_spc 12 298#define bc_config_s_fill_we_offset 3 299#define bc_config_v_fill_we_offset 16 300#define bc_config_s_bc_we_ctl 9 301#define bc_config_v_bc_we_ctl 20 302// cbox registers, continued 303#define ei_stat_s_sys_id 4 304#define ei_stat_v_sys_id 24 305#define ei_stat_v_bc_tperr 28 306#define ei_stat_v_bc_tc_perr 29 307#define ei_stat_v_ei_es 30 308#define ei_stat_v_cor_ecc_err 31 309#define ei_stat_v_unc_ecc_err 32 310#define ei_stat_v_ei_par_err 33 311#define ei_stat_v_fil_ird 34 312#define ei_stat_v_seo_hrd_err 35 313// 314#define bc_tag_addr_v_hit 12 315#define bc_tag_addr_v_tagctl_p 13 316#define bc_tag_addr_v_tagctl_d 14 317#define bc_tag_addr_v_tagctl_s 15 318#define bc_tag_addr_v_tagctl_v 16 319#define bc_tag_addr_v_tag_p 17 320#define bc_tag_addr_s_bc_tag 19 321#define bc_tag_addr_v_bc_tag 20 322// ibox and icache registers. 323#define aster_v_kar 0 324#define aster_v_ear 1 325#define aster_v_sar 2 326#define aster_v_uar 3 327#define astrr_v_kar 0 328#define astrr_v_ear 1 329#define astrr_v_sar 2 330#define astrr_v_uar 3 331#define exc_addr_v_pal 0 332#define exc_sum_v_swc 10 333#define exc_sum_v_inv 11 334#define exc_sum_v_dze 12 335#define exc_sum_v_fov 13 336#define exc_sum_v_unf 14 337#define exc_sum_v_ine 15 338#define exc_sum_v_iov 16 339#define hwint_clr_v_pc0c 27 340#define hwint_clr_v_pc1c 28 341#define hwint_clr_v_pc2c 29 342#define hwint_clr_v_crdc 32 343#define hwint_clr_v_slc 33 344// ibox and icache registers, continued 345#define icperr_stat_v_dpe 11 346#define icperr_stat_v_tpe 12 347#define icperr_stat_v_tmr 13 348#define ic_perr_stat_v_dpe 11 349#define ic_perr_stat_v_tpe 12 350#define ic_perr_stat_v_tmr 13 351#define icsr_v_pma 8 352#define icsr_v_pmp 9 353#define icsr_v_byt 17 354#define icsr_v_fmp 18 355#define icsr_v_im0 20 356#define icsr_v_im1 21 357#define icsr_v_im2 22 358#define icsr_v_im3 23 359#define icsr_v_tmm 24 360#define icsr_v_tmd 25 361#define icsr_v_fpe 26 362#define icsr_v_hwe 27 363#define icsr_s_spe 2 364#define icsr_v_spe 28 365#define icsr_v_sde 30 366#define icsr_v_crde 32 367#define icsr_v_sle 33 368#define icsr_v_fms 34 369#define icsr_v_fbt 35 370#define icsr_v_fbd 36 371#define icsr_v_dbs 37 372#define icsr_v_ista 38 373#define icsr_v_tst 39 374#define ifault_va_form_s_va 30 375#define ifault_va_form_v_va 3 376#define ifault_va_form_s_vptb 31 377#define ifault_va_form_v_vptb 33 378#define ifault_va_form_nt_s_va 19 379#define ifault_va_form_nt_v_va 3 380#define intid_s_intid 5 381#define intid_v_intid 0 382// ibox and icache registers, continued 383#define ipl_s_ipl 5 384#define ipl_v_ipl 0 385#define itb_is_s_va 30 386#define itb_is_v_va 13 387#define itb_asn_s_asn 7 388#define itb_asn_v_asn 4 389#define itb_pte_v_asm 4 390#define itb_pte_s_gh 2 391#define itb_pte_v_gh 5 392#define itb_pte_v_kre 8 393#define itb_pte_v_ere 9 394#define itb_pte_v_sre 10 395#define itb_pte_v_ure 11 396#define itb_pte_s_pfn 27 397#define itb_pte_v_pfn 32 398#define itb_pte_temp_v_asm 13 399#define itb_pte_temp_v_kre 18 400#define itb_pte_temp_v_ere 19 401#define itb_pte_temp_v_sre 20 402#define itb_pte_temp_v_ure 21 403#define itb_pte_temp_s_gh 3 404#define itb_pte_temp_v_gh 29 405#define itb_pte_temp_s_pfn 27 406#define itb_pte_temp_v_pfn 32 407// ibox and icache registers, continued 408#define itb_tag_s_va 30 409#define itb_tag_v_va 13 410#define pal_base_s_pal_base 26 411#define pal_base_v_pal_base 14 412#define pmctr_s_sel2 4 413#define pmctr_v_sel2 0 414#define pmctr_s_sel1 4 415#define pmctr_v_sel1 4 416#define pmctr_v_killk 8 417#define pmctr_v_killp 9 418#define pmctr_s_ctl2 2 419#define pmctr_v_ctl2 10 420#define pmctr_s_ctl1 2 421#define pmctr_v_ctl1 12 422#define pmctr_s_ctl0 2 423#define pmctr_v_ctl0 14 424#define pmctr_s_ctr2 14 425#define pmctr_v_ctr2 16 426#define pmctr_v_killu 30 427#define pmctr_v_sel0 31 428#define pmctr_s_ctr1 16 429#define pmctr_v_ctr1 32 430#define pmctr_s_ctr0 16 431#define pmctr_v_ctr0 48 432#define ps_v_cm0 3 433#define ps_v_cm1 4 434#define isr_s_astrr 4 435#define isr_v_astrr 0 436#define isr_s_sisr 15 437#define isr_v_sisr 4 438#define isr_v_atr 19 439#define isr_v_i20 20 440#define isr_v_i21 21 441#define isr_v_i22 22 442#define isr_v_i23 23 443#define isr_v_pc0 27 444#define isr_v_pc1 28 445#define isr_v_pc2 29 446#define isr_v_pfl 30 447#define isr_v_mck 31 448#define isr_v_crd 32 449#define isr_v_sli 33 450#define isr_v_hlt 34 451#define sirr_s_sirr 15 452#define sirr_v_sirr 4 453// ibox and icache registers, continued 454#define sl_txmit_v_tmt 7 455#define sl_rcv_v_rcv 6 456// mbox and dcache registers. 457#define alt_mode_v_am0 3 458#define alt_mode_v_am1 4 459#define cc_ctl_v_cc_ena 32 460#define dcperr_stat_v_seo 0 461#define dcperr_stat_v_lock 1 462#define dcperr_stat_v_dp0 2 463#define dcperr_stat_v_dp1 3 464#define dcperr_stat_v_tp0 4 465#define dcperr_stat_v_tp1 5 466// the following two registers are used exclusively for test and diagnostics. 467// they should not be referenced in normal operation. 468#define dc_test_ctl_v_bank0 0 469#define dc_test_ctl_v_bank1 1 470#define dc_test_ctl_v_fill_0 2 471#define dc_test_ctl_s_index 10 472#define dc_test_ctl_v_index 3 473#define dc_test_ctl_s_fill_1 19 474#define dc_test_ctl_v_fill_1 13 475#define dc_test_ctl_s_fill_2 32 476#define dc_test_ctl_v_fill_2 32 477// mbox and dcache registers, continued. 478#define dc_test_tag_v_tag_par 2 479#define dc_test_tag_v_ow0 11 480#define dc_test_tag_v_ow1 12 481#define dc_test_tag_s_tag 26 482#define dc_test_tag_v_tag 13 483#define dc_test_tag_temp_v_tag_par 2 484#define dc_test_tag_temp_v_d0p0 3 485#define dc_test_tag_temp_v_d0p1 4 486#define dc_test_tag_temp_v_d1p0 5 487#define dc_test_tag_temp_v_d1p1 6 488#define dc_test_tag_temp_v_ow0 11 489#define dc_test_tag_temp_v_ow1 12 490#define dc_test_tag_temp_s_tag 26 491#define dc_test_tag_temp_v_tag 13 492#define dtb_asn_s_asn 7 493#define dtb_asn_v_asn 57 494#define dtb_cm_v_cm0 3 495#define dtb_cm_v_cm1 4 496#define dtbis_s_va0 30 497#define dtbis_v_va0 13 498#define dtb_pte_v_for 1 499#define dtb_pte_v_fow 2 500#define dtb_pte_v_asm 4 501#define dtb_pte_s_gh 2 502#define dtb_pte_v_gh 5 503#define dtb_pte_v_kre 8 504#define dtb_pte_v_ere 9 505#define dtb_pte_v_sre 10 506#define dtb_pte_v_ure 11 507#define dtb_pte_v_kwe 12 508#define dtb_pte_v_ewe 13 509#define dtb_pte_v_swe 14 510#define dtb_pte_v_uwe 15 511#define dtb_pte_s_pfn 27 512#define dtb_pte_v_pfn 32 513// mbox and dcache registers, continued. 514#define dtb_pte_temp_v_for 0 515#define dtb_pte_temp_v_fow 1 516#define dtb_pte_temp_v_kre 2 517#define dtb_pte_temp_v_ere 3 518#define dtb_pte_temp_v_sre 4 519#define dtb_pte_temp_v_ure 5 520#define dtb_pte_temp_v_kwe 6 521#define dtb_pte_temp_v_ewe 7 522#define dtb_pte_temp_v_swe 8 523#define dtb_pte_temp_v_uwe 9 524#define dtb_pte_temp_v_asm 10 525#define dtb_pte_temp_s_fill_0 2 526#define dtb_pte_temp_v_fill_0 11 527#define dtb_pte_temp_s_pfn 27 528#define dtb_pte_temp_v_pfn 13 529#define dtb_tag_s_va 30 530#define dtb_tag_v_va 13 531// most mcsr bits are used for testability and diagnostics only. 532// for normal operation, they will be supported in the following configuration: 533// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, 534// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 535#define mcsr_v_big_endian 0 536#define mcsr_v_sp0 1 537#define mcsr_v_sp1 2 538#define mcsr_v_mbox_sel 3 539#define mcsr_v_e_big_endian 4 540#define mcsr_v_dbg_packet_sel 5 541#define dc_mode_v_dc_ena 0 542#define dc_mode_v_dc_fhit 1 543#define dc_mode_v_dc_bad_parity 2 544#define dc_mode_v_dc_perr_dis 3 545#define dc_mode_v_dc_doa 4 546#define maf_mode_v_maf_nomerge 0 547#define maf_mode_v_wb_flush_always 1 548#define maf_mode_v_wb_nomerge 2 549#define maf_mode_v_io_nomerge 3 550#define maf_mode_v_wb_cnt_disable 4 551#define maf_mode_v_maf_arb_disable 5 552#define maf_mode_v_dread_pending 6 553#define maf_mode_v_wb_pending 7 554// mbox and dcache registers, continued. 555#define mm_stat_v_wr 0 556#define mm_stat_v_acv 1 557#define mm_stat_v_for 2 558#define mm_stat_v_fow 3 559#define mm_stat_v_dtb_miss 4 560#define mm_stat_v_bad_va 5 561#define mm_stat_s_ra 5 562#define mm_stat_v_ra 6 563#define mm_stat_s_opcode 6 564#define mm_stat_v_opcode 11 565#define mvptbr_s_vptb 31 566#define mvptbr_v_vptb 33 567#define va_form_s_va 30 568#define va_form_v_va 3 569#define va_form_s_vptb 31 570#define va_form_v_vptb 33 571#define va_form_nt_s_va 19 572#define va_form_nt_v_va 3 573//.endm 574 575#endif 576