dc21164FromGasSources.h revision 8012
18012Ssaidi@eecs.umich.edu/* 28012Ssaidi@eecs.umich.eduCopyright 1993 Hewlett-Packard Development Company, L.P. 38012Ssaidi@eecs.umich.edu 48012Ssaidi@eecs.umich.eduPermission is hereby granted, free of charge, to any person obtaining a copy of 58012Ssaidi@eecs.umich.eduthis software and associated documentation files (the "Software"), to deal in 68012Ssaidi@eecs.umich.eduthe Software without restriction, including without limitation the rights to 78012Ssaidi@eecs.umich.eduuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 88012Ssaidi@eecs.umich.eduof the Software, and to permit persons to whom the Software is furnished to do 98012Ssaidi@eecs.umich.eduso, subject to the following conditions: 108012Ssaidi@eecs.umich.edu 118012Ssaidi@eecs.umich.eduThe above copyright notice and this permission notice shall be included in all 128012Ssaidi@eecs.umich.educopies or substantial portions of the Software. 138012Ssaidi@eecs.umich.edu 148012Ssaidi@eecs.umich.eduTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158012Ssaidi@eecs.umich.eduIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168012Ssaidi@eecs.umich.eduFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 178012Ssaidi@eecs.umich.eduAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 188012Ssaidi@eecs.umich.eduLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 198012Ssaidi@eecs.umich.eduOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 208012Ssaidi@eecs.umich.eduSOFTWARE. 218012Ssaidi@eecs.umich.edu*/ 228012Ssaidi@eecs.umich.edu 237997Ssaidi@eecs.umich.edu#ifndef DC21164FROMGASSOURCES_INCLUDED 247997Ssaidi@eecs.umich.edu#define DC21164FROMGASSOURCES_INCLUDED 1 257997Ssaidi@eecs.umich.edu 267997Ssaidi@eecs.umich.edu/* 277997Ssaidi@eecs.umich.edu** 287997Ssaidi@eecs.umich.edu** FACILITY: 297997Ssaidi@eecs.umich.edu** 307997Ssaidi@eecs.umich.edu** DECchip 21164 PALcode 317997Ssaidi@eecs.umich.edu** 327997Ssaidi@eecs.umich.edu** MODULE: 337997Ssaidi@eecs.umich.edu** 347997Ssaidi@eecs.umich.edu** dc21164.h 357997Ssaidi@eecs.umich.edu** 367997Ssaidi@eecs.umich.edu** MODULE DESCRIPTION: 377997Ssaidi@eecs.umich.edu** 387997Ssaidi@eecs.umich.edu** DECchip 21164 specific definitions 397997Ssaidi@eecs.umich.edu** 407997Ssaidi@eecs.umich.edu** AUTHOR: ER 417997Ssaidi@eecs.umich.edu** 427997Ssaidi@eecs.umich.edu** CREATION DATE: 24-Nov-1993 437997Ssaidi@eecs.umich.edu** 447997Ssaidi@eecs.umich.edu** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 457997Ssaidi@eecs.umich.edu** 467997Ssaidi@eecs.umich.edu** MODIFICATION HISTORY: 477997Ssaidi@eecs.umich.edu** 487997Ssaidi@eecs.umich.edu** $Log: dc21164FromGasSources.h,v $ 497997Ssaidi@eecs.umich.edu** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 507997Ssaidi@eecs.umich.edu** current 10/29/97 517997Ssaidi@eecs.umich.edu** 527997Ssaidi@eecs.umich.edu** Revision 1.1 1995/11/18 01:45:46 boyle 537997Ssaidi@eecs.umich.edu** Initial revision 547997Ssaidi@eecs.umich.edu** 557997Ssaidi@eecs.umich.edu** Revision 1.15 1995/04/21 02:06:30 fdh 567997Ssaidi@eecs.umich.edu** Replaced C++ style comments with Standard C style comments. 577997Ssaidi@eecs.umich.edu** 587997Ssaidi@eecs.umich.edu** Revision 1.14 1995/03/20 14:55:23 samberg 597997Ssaidi@eecs.umich.edu** Add flushIc to make Roger Cruz's life easier. 607997Ssaidi@eecs.umich.edu** 617997Ssaidi@eecs.umich.edu** Revision 1.13 1994/12/14 15:52:48 samberg 627997Ssaidi@eecs.umich.edu** Add slXmit and slRcv bit definitions 637997Ssaidi@eecs.umich.edu** 647997Ssaidi@eecs.umich.edu** Revision 1.12 1994/09/07 15:43:49 samberg 657997Ssaidi@eecs.umich.edu** Changes for Makefile.vpp, take out OSF definition 667997Ssaidi@eecs.umich.edu** 677997Ssaidi@eecs.umich.edu** Revision 1.11 1994/07/26 17:38:35 samberg 687997Ssaidi@eecs.umich.edu** Changes for SD164. 697997Ssaidi@eecs.umich.edu** 707997Ssaidi@eecs.umich.edu** Revision 1.10 1994/07/08 17:02:12 samberg 717997Ssaidi@eecs.umich.edu** Changes to support platform specific additions 727997Ssaidi@eecs.umich.edu** 737997Ssaidi@eecs.umich.edu** Revision 1.8 1994/05/31 15:49:21 ericr 747997Ssaidi@eecs.umich.edu** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows 757997Ssaidi@eecs.umich.edu** 767997Ssaidi@eecs.umich.edu** Revision 1.7 1994/05/26 19:29:51 ericr 777997Ssaidi@eecs.umich.edu** Added BC_CONFIG definitions 787997Ssaidi@eecs.umich.edu** 797997Ssaidi@eecs.umich.edu** Revision 1.6 1994/05/25 14:27:25 ericr 807997Ssaidi@eecs.umich.edu** Added physical bit to ldq_lp and stq_cp macros 817997Ssaidi@eecs.umich.edu** 827997Ssaidi@eecs.umich.edu** Revision 1.5 1994/05/20 18:07:50 ericr 837997Ssaidi@eecs.umich.edu** Changed line comments to C++ style comment character 847997Ssaidi@eecs.umich.edu** 857997Ssaidi@eecs.umich.edu** Revision 1.4 1994/01/17 21:46:54 ericr 867997Ssaidi@eecs.umich.edu** Added floating point register definitions 877997Ssaidi@eecs.umich.edu** 887997Ssaidi@eecs.umich.edu** Revision 1.3 1994/01/03 19:31:49 ericr 897997Ssaidi@eecs.umich.edu** Added cache parity error status register definitions 907997Ssaidi@eecs.umich.edu** 917997Ssaidi@eecs.umich.edu** Revision 1.2 1993/12/22 20:42:35 eric 927997Ssaidi@eecs.umich.edu** Added ptTrap, ptMisc and flag definitions 937997Ssaidi@eecs.umich.edu** Added PAL shadow regsiter definitions 947997Ssaidi@eecs.umich.edu** 957997Ssaidi@eecs.umich.edu** Revision 1.1 1993/12/16 21:55:05 eric 967997Ssaidi@eecs.umich.edu** Initial revision 977997Ssaidi@eecs.umich.edu** 987997Ssaidi@eecs.umich.edu** 997997Ssaidi@eecs.umich.edu**-- 1007997Ssaidi@eecs.umich.edu*/ 1017997Ssaidi@eecs.umich.edu 1027997Ssaidi@eecs.umich.edu 1037997Ssaidi@eecs.umich.edu/* 1047997Ssaidi@eecs.umich.edu** 1057997Ssaidi@eecs.umich.edu** INTERNAL PROCESSOR REGISTER DEFINITIONS 1067997Ssaidi@eecs.umich.edu** 1077997Ssaidi@eecs.umich.edu** The internal processor register definitions below are annotated 1087997Ssaidi@eecs.umich.edu** with one of the following symbols: 1097997Ssaidi@eecs.umich.edu** 1107997Ssaidi@eecs.umich.edu** RW - The register may be read and written 1117997Ssaidi@eecs.umich.edu** RO - The register may only be read 1127997Ssaidi@eecs.umich.edu** WO - The register may only be written 1137997Ssaidi@eecs.umich.edu** 1147997Ssaidi@eecs.umich.edu** For RO and WO registers, all bits and fields within the register are 1157997Ssaidi@eecs.umich.edu** also read-only or write-only. For RW registers, each bit or field 1167997Ssaidi@eecs.umich.edu** within the register is annotated with one of the following: 1177997Ssaidi@eecs.umich.edu** 1187997Ssaidi@eecs.umich.edu** RW - The bit/field may be read and written 1197997Ssaidi@eecs.umich.edu** RO - The bit/field may be read; writes are ignored 1207997Ssaidi@eecs.umich.edu** WO - The bit/field may be written; reads return UNPREDICTABLE 1217997Ssaidi@eecs.umich.edu** WZ - The bit/field may be written; reads return a zero value 1227997Ssaidi@eecs.umich.edu** W0C - The bit/field may be read; write-zero-to-clear 1237997Ssaidi@eecs.umich.edu** W1C - The bit/field may be read; write-one-to-clear 1247997Ssaidi@eecs.umich.edu** WA - The bit/field may be read; write-anything-to-clear 1257997Ssaidi@eecs.umich.edu** RC - The bit/field may be read, causing state to clear; 1267997Ssaidi@eecs.umich.edu** writes are ignored 1277997Ssaidi@eecs.umich.edu** 1287997Ssaidi@eecs.umich.edu*/ 1297997Ssaidi@eecs.umich.edu 1307997Ssaidi@eecs.umich.edu 1317997Ssaidi@eecs.umich.edu/* 1327997Ssaidi@eecs.umich.edu** 1337997Ssaidi@eecs.umich.edu** Ibox IPR Definitions: 1347997Ssaidi@eecs.umich.edu** 1357997Ssaidi@eecs.umich.edu*/ 1367997Ssaidi@eecs.umich.edu 1377997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 1387997Ssaidi@eecs.umich.edu#define itbTag 0x101 /* WO - ITB Tag */ 1397997Ssaidi@eecs.umich.edu#define itbPte 0x102 /* RW - ITB Page Table Entry */ 1407997Ssaidi@eecs.umich.edu#define itbAsn 0x103 /* RW - ITB Address Space Number */ 1417997Ssaidi@eecs.umich.edu#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 1427997Ssaidi@eecs.umich.edu#define itbIa 0x105 /* WO - ITB Invalidate All */ 1437997Ssaidi@eecs.umich.edu#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 1447997Ssaidi@eecs.umich.edu#define itbIs 0x107 /* WO - ITB Invalidate Single */ 1457997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 1467997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 1477997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 1487997Ssaidi@eecs.umich.edu#define excAddr 0x10B /* RW - Exception Address */ 1497997Ssaidi@eecs.umich.edu#define excSum 0x10C /* RW - Exception Summary */ 1507997Ssaidi@eecs.umich.edu#define excMask 0x10D /* RO - Exception Mask */ 1517997Ssaidi@eecs.umich.edu#define palBase 0x10E /* RW - PAL Base */ 1527997Ssaidi@eecs.umich.edu#define ips 0x10F /* RW - Processor Status */ 1537997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 1547997Ssaidi@eecs.umich.edu#define intId 0x111 /* RO - Interrupt ID */ 1557997Ssaidi@eecs.umich.edu#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 1567997Ssaidi@eecs.umich.edu#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 1577997Ssaidi@eecs.umich.edu#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 1587997Ssaidi@eecs.umich.edu#define slXmit 0x116 /* WO - Serial Line Transmit */ 1597997Ssaidi@eecs.umich.edu#define slRcv 0x117 /* RO - Serial Line Receive */ 1607997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 1617997Ssaidi@eecs.umich.edu#define icFlush 0x119 /* WO - I-Cache Flush Control */ 1627997Ssaidi@eecs.umich.edu#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 1637997Ssaidi@eecs.umich.edu#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 1647997Ssaidi@eecs.umich.edu#define PmCtr 0x11C /* RW - Performance Counter */ 1657997Ssaidi@eecs.umich.edu 1667997Ssaidi@eecs.umich.edu/* 1677997Ssaidi@eecs.umich.edu** 1687997Ssaidi@eecs.umich.edu** Ibox Control/Status Register (ICSR) Bit Summary 1697997Ssaidi@eecs.umich.edu** 1707997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1717997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 1727997Ssaidi@eecs.umich.edu** <39> 1 TST RW,0 Assert Test Status 1737997Ssaidi@eecs.umich.edu** <38> 1 ISTA RO I-Cache BIST Status 1747997Ssaidi@eecs.umich.edu** <37> 1 DBS RW,1 Debug Port Select 1757997Ssaidi@eecs.umich.edu** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 1767997Ssaidi@eecs.umich.edu** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 1777997Ssaidi@eecs.umich.edu** <34> 1 FMS RW,0 Force I-Cache Miss 1787997Ssaidi@eecs.umich.edu** <33> 1 SLE RW,0 Enable Serial Line Interrupts 1797997Ssaidi@eecs.umich.edu** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 1807997Ssaidi@eecs.umich.edu** <30> 1 SDE RW,0 Enable PAL Shadow Registers 1817997Ssaidi@eecs.umich.edu** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 1827997Ssaidi@eecs.umich.edu** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 1837997Ssaidi@eecs.umich.edu** <26> 1 FPE RW,0 Enable Floating Point Instructions 1847997Ssaidi@eecs.umich.edu** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 1857997Ssaidi@eecs.umich.edu** <24> 1 TMM RW,0 Timeout Counter Mode 1867997Ssaidi@eecs.umich.edu** 1877997Ssaidi@eecs.umich.edu*/ 1887997Ssaidi@eecs.umich.edu 1897997Ssaidi@eecs.umich.edu#define ICSR_V_TST 39 1907997Ssaidi@eecs.umich.edu#define ICSR_M_TST (1<<ICSR_V_TST) 1917997Ssaidi@eecs.umich.edu#define ICSR_V_ISTA 38 1927997Ssaidi@eecs.umich.edu#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 1937997Ssaidi@eecs.umich.edu#define ICSR_V_DBS 37 1947997Ssaidi@eecs.umich.edu#define ICSR_M_DBS (1<<ICSR_V_DBS) 1957997Ssaidi@eecs.umich.edu#define ICSR_V_FBD 36 1967997Ssaidi@eecs.umich.edu#define ICSR_M_FBD (1<<ICSR_V_FBD) 1977997Ssaidi@eecs.umich.edu#define ICSR_V_FBT 35 1987997Ssaidi@eecs.umich.edu#define ICSR_M_FBT (1<<ICSR_V_FBT) 1997997Ssaidi@eecs.umich.edu#define ICSR_V_FMS 34 2007997Ssaidi@eecs.umich.edu#define ICSR_M_FMS (1<<ICSR_V_FMS) 2017997Ssaidi@eecs.umich.edu#define ICSR_V_SLE 33 2027997Ssaidi@eecs.umich.edu#define ICSR_M_SLE (1<<ICSR_V_SLE) 2037997Ssaidi@eecs.umich.edu#define ICSR_V_CRDE 32 2047997Ssaidi@eecs.umich.edu#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 2057997Ssaidi@eecs.umich.edu#define ICSR_V_SDE 30 2067997Ssaidi@eecs.umich.edu#define ICSR_M_SDE (1<<ICSR_V_SDE) 2077997Ssaidi@eecs.umich.edu#define ICSR_V_SPE 28 2087997Ssaidi@eecs.umich.edu#define ICSR_M_SPE (3<<ICSR_V_SPE) 2097997Ssaidi@eecs.umich.edu#define ICSR_V_HWE 27 2107997Ssaidi@eecs.umich.edu#define ICSR_M_HWE (1<<ICSR_V_HWE) 2117997Ssaidi@eecs.umich.edu#define ICSR_V_FPE 26 2127997Ssaidi@eecs.umich.edu#define ICSR_M_FPE (1<<ICSR_V_FPE) 2137997Ssaidi@eecs.umich.edu#define ICSR_V_TMD 25 2147997Ssaidi@eecs.umich.edu#define ICSR_M_TMD (1<<ICSR_V_TMD) 2157997Ssaidi@eecs.umich.edu#define ICSR_V_TMM 24 2167997Ssaidi@eecs.umich.edu#define ICSR_M_TMM (1<<ICSR_V_TMM) 2177997Ssaidi@eecs.umich.edu 2187997Ssaidi@eecs.umich.edu/* 2197997Ssaidi@eecs.umich.edu** 2207997Ssaidi@eecs.umich.edu** Serial Line Tranmit Register (SL_XMIT) 2217997Ssaidi@eecs.umich.edu** 2227997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2237997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 2247997Ssaidi@eecs.umich.edu** <7> 1 TMT WO,1 Serial line transmit data 2257997Ssaidi@eecs.umich.edu** 2267997Ssaidi@eecs.umich.edu*/ 2277997Ssaidi@eecs.umich.edu 2287997Ssaidi@eecs.umich.edu#define SLXMIT_V_TMT 7 2297997Ssaidi@eecs.umich.edu#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 2307997Ssaidi@eecs.umich.edu 2317997Ssaidi@eecs.umich.edu/* 2327997Ssaidi@eecs.umich.edu** 2337997Ssaidi@eecs.umich.edu** Serial Line Receive Register (SL_RCV) 2347997Ssaidi@eecs.umich.edu** 2357997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2367997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 2377997Ssaidi@eecs.umich.edu** <6> 1 RCV RO Serial line receive data 2387997Ssaidi@eecs.umich.edu** 2397997Ssaidi@eecs.umich.edu*/ 2407997Ssaidi@eecs.umich.edu 2417997Ssaidi@eecs.umich.edu#define SLRCV_V_RCV 6 2427997Ssaidi@eecs.umich.edu#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 2437997Ssaidi@eecs.umich.edu 2447997Ssaidi@eecs.umich.edu/* 2457997Ssaidi@eecs.umich.edu** 2467997Ssaidi@eecs.umich.edu** Icache Parity Error Status Register (ICPERR) Bit Summary 2477997Ssaidi@eecs.umich.edu** 2487997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2497997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 2507997Ssaidi@eecs.umich.edu** <13> 1 TMR W1C Timeout reset error 2517997Ssaidi@eecs.umich.edu** <12> 1 TPE W1C Tag parity error 2527997Ssaidi@eecs.umich.edu** <11> 1 DPE W1C Data parity error 2537997Ssaidi@eecs.umich.edu** 2547997Ssaidi@eecs.umich.edu*/ 2557997Ssaidi@eecs.umich.edu 2567997Ssaidi@eecs.umich.edu#define ICPERR_V_TMR 13 2577997Ssaidi@eecs.umich.edu#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 2587997Ssaidi@eecs.umich.edu#define ICPERR_V_TPE 12 2597997Ssaidi@eecs.umich.edu#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 2607997Ssaidi@eecs.umich.edu#define ICPERR_V_DPE 11 2617997Ssaidi@eecs.umich.edu#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 2627997Ssaidi@eecs.umich.edu 2637997Ssaidi@eecs.umich.edu#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 2647997Ssaidi@eecs.umich.edu 2657997Ssaidi@eecs.umich.edu/* 2667997Ssaidi@eecs.umich.edu** 2677997Ssaidi@eecs.umich.edu** Exception Summary Register (EXC_SUM) Bit Summary 2687997Ssaidi@eecs.umich.edu** 2697997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2707997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 2717997Ssaidi@eecs.umich.edu** <16> 1 IOV WA Integer overflow 2727997Ssaidi@eecs.umich.edu** <15> 1 INE WA Inexact result 2737997Ssaidi@eecs.umich.edu** <14> 1 UNF WA Underflow 2747997Ssaidi@eecs.umich.edu** <13> 1 FOV WA Overflow 2757997Ssaidi@eecs.umich.edu** <12> 1 DZE WA Division by zero 2767997Ssaidi@eecs.umich.edu** <11> 1 INV WA Invalid operation 2777997Ssaidi@eecs.umich.edu** <10> 1 SWC WA Software completion 2787997Ssaidi@eecs.umich.edu** 2797997Ssaidi@eecs.umich.edu*/ 2807997Ssaidi@eecs.umich.edu 2817997Ssaidi@eecs.umich.edu#define EXC_V_IOV 16 2827997Ssaidi@eecs.umich.edu#define EXC_M_IOV (1<<EXC_V_IOV) 2837997Ssaidi@eecs.umich.edu#define EXC_V_INE 15 2847997Ssaidi@eecs.umich.edu#define EXC_M_INE (1<<EXC_V_INE) 2857997Ssaidi@eecs.umich.edu#define EXC_V_UNF 14 2867997Ssaidi@eecs.umich.edu#define EXC_M_UNF (1<<EXC_V_UNF) 2877997Ssaidi@eecs.umich.edu#define EXC_V_FOV 13 2887997Ssaidi@eecs.umich.edu#define EXC_M_FOV (1<<EXC_V_FOV) 2897997Ssaidi@eecs.umich.edu#define EXC_V_DZE 12 2907997Ssaidi@eecs.umich.edu#define EXC_M_DZE (1<<EXC_V_DZE) 2917997Ssaidi@eecs.umich.edu#define EXC_V_INV 11 2927997Ssaidi@eecs.umich.edu#define EXC_M_INV (1<<EXC_V_INV) 2937997Ssaidi@eecs.umich.edu#define EXC_V_SWC 10 2947997Ssaidi@eecs.umich.edu#define EXC_M_SWC (1<<EXC_V_SWC) 2957997Ssaidi@eecs.umich.edu 2967997Ssaidi@eecs.umich.edu/* 2977997Ssaidi@eecs.umich.edu** 2987997Ssaidi@eecs.umich.edu** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 2997997Ssaidi@eecs.umich.edu** 3007997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 3017997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 3027997Ssaidi@eecs.umich.edu** <33> 1 SLC W1C Clear Serial Line interrupt 3037997Ssaidi@eecs.umich.edu** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 3047997Ssaidi@eecs.umich.edu** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 3057997Ssaidi@eecs.umich.edu** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 3067997Ssaidi@eecs.umich.edu** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 3077997Ssaidi@eecs.umich.edu** 3087997Ssaidi@eecs.umich.edu*/ 3097997Ssaidi@eecs.umich.edu 3107997Ssaidi@eecs.umich.edu#define HWINT_V_SLC 33 3117997Ssaidi@eecs.umich.edu#define HWINT_M_SLC (1<<HWINT_V_SLC) 3127997Ssaidi@eecs.umich.edu#define HWINT_V_CRDC 32 3137997Ssaidi@eecs.umich.edu#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 3147997Ssaidi@eecs.umich.edu#define HWINT_V_PC2C 29 3157997Ssaidi@eecs.umich.edu#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 3167997Ssaidi@eecs.umich.edu#define HWINT_V_PC1C 28 3177997Ssaidi@eecs.umich.edu#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 3187997Ssaidi@eecs.umich.edu#define HWINT_V_PC0C 27 3197997Ssaidi@eecs.umich.edu#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 3207997Ssaidi@eecs.umich.edu 3217997Ssaidi@eecs.umich.edu/* 3227997Ssaidi@eecs.umich.edu** 3237997Ssaidi@eecs.umich.edu** Interrupt Summary Register (ISR) Bit Summary 3247997Ssaidi@eecs.umich.edu** 3257997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 3267997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 3277997Ssaidi@eecs.umich.edu** <34> 1 HLT RO External Halt interrupt 3287997Ssaidi@eecs.umich.edu** <33> 1 SLI RO Serial Line interrupt 3297997Ssaidi@eecs.umich.edu** <32> 1 CRD RO Correctable ECC errors 3307997Ssaidi@eecs.umich.edu** <31> 1 MCK RO System Machine Check 3317997Ssaidi@eecs.umich.edu** <30> 1 PFL RO Power Fail 3327997Ssaidi@eecs.umich.edu** <29> 1 PC2 RO Performance Counter 2 interrupt 3337997Ssaidi@eecs.umich.edu** <28> 1 PC1 RO Performance Counter 1 interrupt 3347997Ssaidi@eecs.umich.edu** <27> 1 PC0 RO Performance Counter 0 interrupt 3357997Ssaidi@eecs.umich.edu** <23> 1 I23 RO External Hardware interrupt 3367997Ssaidi@eecs.umich.edu** <22> 1 I22 RO External Hardware interrupt 3377997Ssaidi@eecs.umich.edu** <21> 1 I21 RO External Hardware interrupt 3387997Ssaidi@eecs.umich.edu** <20> 1 I20 RO External Hardware interrupt 3397997Ssaidi@eecs.umich.edu** <19> 1 ATR RO Async. System Trap request 3407997Ssaidi@eecs.umich.edu** <18:4> 15 SIRR RO,0 Software Interrupt request 3417997Ssaidi@eecs.umich.edu** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 3427997Ssaidi@eecs.umich.edu** 3437997Ssaidi@eecs.umich.edu**/ 3447997Ssaidi@eecs.umich.edu 3457997Ssaidi@eecs.umich.edu#define ISR_V_HLT 34 3467997Ssaidi@eecs.umich.edu#define ISR_M_HLT (1<<ISR_V_HLT) 3477997Ssaidi@eecs.umich.edu#define ISR_V_SLI 33 3487997Ssaidi@eecs.umich.edu#define ISR_M_SLI (1<<ISR_V_SLI) 3497997Ssaidi@eecs.umich.edu#define ISR_V_CRD 32 3507997Ssaidi@eecs.umich.edu#define ISR_M_CRD (1<<ISR_V_CRD) 3517997Ssaidi@eecs.umich.edu#define ISR_V_MCK 31 3527997Ssaidi@eecs.umich.edu#define ISR_M_MCK (1<<ISR_V_MCK) 3537997Ssaidi@eecs.umich.edu#define ISR_V_PFL 30 3547997Ssaidi@eecs.umich.edu#define ISR_M_PFL (1<<ISR_V_PFL) 3557997Ssaidi@eecs.umich.edu#define ISR_V_PC2 29 3567997Ssaidi@eecs.umich.edu#define ISR_M_PC2 (1<<ISR_V_PC2) 3577997Ssaidi@eecs.umich.edu#define ISR_V_PC1 28 3587997Ssaidi@eecs.umich.edu#define ISR_M_PC1 (1<<ISR_V_PC1) 3597997Ssaidi@eecs.umich.edu#define ISR_V_PC0 27 3607997Ssaidi@eecs.umich.edu#define ISR_M_PC0 (1<<ISR_V_PC0) 3617997Ssaidi@eecs.umich.edu#define ISR_V_I23 23 3627997Ssaidi@eecs.umich.edu#define ISR_M_I23 (1<<ISR_V_I23) 3637997Ssaidi@eecs.umich.edu#define ISR_V_I22 22 3647997Ssaidi@eecs.umich.edu#define ISR_M_I22 (1<<ISR_V_I22) 3657997Ssaidi@eecs.umich.edu#define ISR_V_I21 21 3667997Ssaidi@eecs.umich.edu#define ISR_M_I21 (1<<ISR_V_I21) 3677997Ssaidi@eecs.umich.edu#define ISR_V_I20 20 3687997Ssaidi@eecs.umich.edu#define ISR_M_I20 (1<<ISR_V_I20) 3697997Ssaidi@eecs.umich.edu#define ISR_V_ATR 19 3707997Ssaidi@eecs.umich.edu#define ISR_M_ATR (1<<ISR_V_ATR) 3717997Ssaidi@eecs.umich.edu#define ISR_V_SIRR 4 3727997Ssaidi@eecs.umich.edu#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 3737997Ssaidi@eecs.umich.edu#define ISR_V_ASTRR 0 3747997Ssaidi@eecs.umich.edu#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 3757997Ssaidi@eecs.umich.edu 3767997Ssaidi@eecs.umich.edu/* 3777997Ssaidi@eecs.umich.edu** 3787997Ssaidi@eecs.umich.edu** Mbox and D-Cache IPR Definitions: 3797997Ssaidi@eecs.umich.edu** 3807997Ssaidi@eecs.umich.edu*/ 3817997Ssaidi@eecs.umich.edu 3827997Ssaidi@eecs.umich.edu#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 3837997Ssaidi@eecs.umich.edu#define dtbCm 0x201 /* WO - DTB Current Mode */ 3847997Ssaidi@eecs.umich.edu#define dtbTag 0x202 /* WO - DTB Tag */ 3857997Ssaidi@eecs.umich.edu#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 3867997Ssaidi@eecs.umich.edu#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 3877997Ssaidi@eecs.umich.edu#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 3887997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 3897997Ssaidi@eecs.umich.edu#define vaForm 0x207 /* RO - Formatted Virtual Address */ 3907997Ssaidi@eecs.umich.edu#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 3917997Ssaidi@eecs.umich.edu#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 3927997Ssaidi@eecs.umich.edu#define dtbIa 0x20A /* WO - DTB Invalidate All */ 3937997Ssaidi@eecs.umich.edu#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 3947997Ssaidi@eecs.umich.edu#define altMode 0x20C /* WO - Alternate Mode */ 3957997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 3967997Ssaidi@eecs.umich.edu#define ccCtl 0x20E /* WO - Cycle Counter Control */ 3977997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 3987997Ssaidi@eecs.umich.edu#define dcFlush 0x210 /* WO - Dcache Flush */ 3997997Ssaidi@eecs.umich.edu#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 4007997Ssaidi@eecs.umich.edu#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 4017997Ssaidi@eecs.umich.edu#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 4027997Ssaidi@eecs.umich.edu#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 4037997Ssaidi@eecs.umich.edu#define dcMode 0x216 /* RW - Dcache Mode */ 4047997Ssaidi@eecs.umich.edu#define mafMode 0x217 /* RW - Miss Address File Mode */ 4057997Ssaidi@eecs.umich.edu 4067997Ssaidi@eecs.umich.edu/* 4077997Ssaidi@eecs.umich.edu** 4087997Ssaidi@eecs.umich.edu** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 4097997Ssaidi@eecs.umich.edu** 4107997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4117997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 4127997Ssaidi@eecs.umich.edu** <16:11> 6 OPCODE RO Opcode of faulting instruction 4137997Ssaidi@eecs.umich.edu** <10:06> 5 RA RO Ra field of faulting instruction 4147997Ssaidi@eecs.umich.edu** <5> 1 BAD_VA RO Bad virtual address 4157997Ssaidi@eecs.umich.edu** <4> 1 DTB_MISS RO Reference resulted in DTB miss 4167997Ssaidi@eecs.umich.edu** <3> 1 FOW RO Fault on write 4177997Ssaidi@eecs.umich.edu** <2> 1 FOR RO Fault on read 4187997Ssaidi@eecs.umich.edu** <1> 1 ACV RO Access violation 4197997Ssaidi@eecs.umich.edu** <0> 1 WR RO Reference type 4207997Ssaidi@eecs.umich.edu** 4217997Ssaidi@eecs.umich.edu*/ 4227997Ssaidi@eecs.umich.edu 4237997Ssaidi@eecs.umich.edu#define MMSTAT_V_OPC 11 4247997Ssaidi@eecs.umich.edu#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 4257997Ssaidi@eecs.umich.edu#define MMSTAT_V_RA 6 4267997Ssaidi@eecs.umich.edu#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 4277997Ssaidi@eecs.umich.edu#define MMSTAT_V_BAD_VA 5 4287997Ssaidi@eecs.umich.edu#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 4297997Ssaidi@eecs.umich.edu#define MMSTAT_V_DTB_MISS 4 4307997Ssaidi@eecs.umich.edu#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 4317997Ssaidi@eecs.umich.edu#define MMSTAT_V_FOW 3 4327997Ssaidi@eecs.umich.edu#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 4337997Ssaidi@eecs.umich.edu#define MMSTAT_V_FOR 2 4347997Ssaidi@eecs.umich.edu#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 4357997Ssaidi@eecs.umich.edu#define MMSTAT_V_ACV 1 4367997Ssaidi@eecs.umich.edu#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 4377997Ssaidi@eecs.umich.edu#define MMSTAT_V_WR 0 4387997Ssaidi@eecs.umich.edu#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 4397997Ssaidi@eecs.umich.edu 4407997Ssaidi@eecs.umich.edu 4417997Ssaidi@eecs.umich.edu/* 4427997Ssaidi@eecs.umich.edu** 4437997Ssaidi@eecs.umich.edu** Mbox Control Register (MCSR) Bit Summary 4447997Ssaidi@eecs.umich.edu** 4457997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4467997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 4477997Ssaidi@eecs.umich.edu** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 4487997Ssaidi@eecs.umich.edu** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 4497997Ssaidi@eecs.umich.edu** <3> 1 DBG0 RW,0 Debug Test Select 4507997Ssaidi@eecs.umich.edu** <2:1> 2 SP RW,0 Superpage mode enable 4517997Ssaidi@eecs.umich.edu** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 4527997Ssaidi@eecs.umich.edu** 4537997Ssaidi@eecs.umich.edu*/ 4547997Ssaidi@eecs.umich.edu 4557997Ssaidi@eecs.umich.edu#define MCSR_V_DBG1 5 4567997Ssaidi@eecs.umich.edu#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 4577997Ssaidi@eecs.umich.edu#define MCSR_V_E_BE 4 4587997Ssaidi@eecs.umich.edu#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 4597997Ssaidi@eecs.umich.edu#define MCSR_V_DBG0 3 4607997Ssaidi@eecs.umich.edu#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 4617997Ssaidi@eecs.umich.edu#define MCSR_V_SP 1 4627997Ssaidi@eecs.umich.edu#define MCSR_M_SP (3<<MCSR_V_SP) 4637997Ssaidi@eecs.umich.edu#define MCSR_V_M_BE 0 4647997Ssaidi@eecs.umich.edu#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 4657997Ssaidi@eecs.umich.edu 4667997Ssaidi@eecs.umich.edu/* 4677997Ssaidi@eecs.umich.edu** 4687997Ssaidi@eecs.umich.edu** Dcache Parity Error Status Register (DCPERR) Bit Summary 4697997Ssaidi@eecs.umich.edu** 4707997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4717997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 4727997Ssaidi@eecs.umich.edu** <5> 1 TP1 RO Dcache bank 1 tag parity error 4737997Ssaidi@eecs.umich.edu** <4> 1 TP0 RO Dcache bank 0 tag parity error 4747997Ssaidi@eecs.umich.edu** <3> 1 DP1 RO Dcache bank 1 data parity error 4757997Ssaidi@eecs.umich.edu** <2> 1 DP0 RO Dcache bank 0 data parity error 4767997Ssaidi@eecs.umich.edu** <1> 1 LOCK W1C Locks/clears bits <5:2> 4777997Ssaidi@eecs.umich.edu** <0> 1 SEO W1C Second Dcache parity error occurred 4787997Ssaidi@eecs.umich.edu** 4797997Ssaidi@eecs.umich.edu*/ 4807997Ssaidi@eecs.umich.edu 4817997Ssaidi@eecs.umich.edu#define DCPERR_V_TP1 5 4827997Ssaidi@eecs.umich.edu#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 4837997Ssaidi@eecs.umich.edu#define DCPERR_V_TP0 4 4847997Ssaidi@eecs.umich.edu#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 4857997Ssaidi@eecs.umich.edu#define DCPERR_V_DP1 3 4867997Ssaidi@eecs.umich.edu#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 4877997Ssaidi@eecs.umich.edu#define DCPERR_V_DP0 2 4887997Ssaidi@eecs.umich.edu#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 4897997Ssaidi@eecs.umich.edu#define DCPERR_V_LOCK 1 4907997Ssaidi@eecs.umich.edu#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 4917997Ssaidi@eecs.umich.edu#define DCPERR_V_SEO 0 4927997Ssaidi@eecs.umich.edu#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 4937997Ssaidi@eecs.umich.edu 4947997Ssaidi@eecs.umich.edu#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 4957997Ssaidi@eecs.umich.edu 4967997Ssaidi@eecs.umich.edu/* 4977997Ssaidi@eecs.umich.edu** 4987997Ssaidi@eecs.umich.edu** Dcache Mode Register (DC_MODE) Bit Summary 4997997Ssaidi@eecs.umich.edu** 5007997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5017997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5027997Ssaidi@eecs.umich.edu** <4> 1 DOA RO Hardware Dcache Disable 5037997Ssaidi@eecs.umich.edu** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 5047997Ssaidi@eecs.umich.edu** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 5057997Ssaidi@eecs.umich.edu** <1> 1 FHIT RW,0 Force Dcache hit 5067997Ssaidi@eecs.umich.edu** <0> 1 ENA RW,0 Software Dcache Enable 5077997Ssaidi@eecs.umich.edu** 5087997Ssaidi@eecs.umich.edu*/ 5097997Ssaidi@eecs.umich.edu 5107997Ssaidi@eecs.umich.edu#define DC_V_DOA 4 5117997Ssaidi@eecs.umich.edu#define DC_M_DOA (1<<DC_V_DOA) 5127997Ssaidi@eecs.umich.edu#define DC_V_PERR_DIS 3 5137997Ssaidi@eecs.umich.edu#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 5147997Ssaidi@eecs.umich.edu#define DC_V_BAD_DP 2 5157997Ssaidi@eecs.umich.edu#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 5167997Ssaidi@eecs.umich.edu#define DC_V_FHIT 1 5177997Ssaidi@eecs.umich.edu#define DC_M_FHIT (1<<DC_V_FHIT) 5187997Ssaidi@eecs.umich.edu#define DC_V_ENA 0 5197997Ssaidi@eecs.umich.edu#define DC_M_ENA (1<<DC_V_ENA) 5207997Ssaidi@eecs.umich.edu 5217997Ssaidi@eecs.umich.edu/* 5227997Ssaidi@eecs.umich.edu** 5237997Ssaidi@eecs.umich.edu** Miss Address File Mode Register (MAF_MODE) Bit Summay 5247997Ssaidi@eecs.umich.edu** 5257997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5267997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5277997Ssaidi@eecs.umich.edu** <7> 1 WB RO,0 If set, pending WB request 5287997Ssaidi@eecs.umich.edu** <6> 1 DREAD RO,0 If set, pending D-read request 5297997Ssaidi@eecs.umich.edu** 5307997Ssaidi@eecs.umich.edu*/ 5317997Ssaidi@eecs.umich.edu 5327997Ssaidi@eecs.umich.edu#define MAF_V_WB_PENDING 7 5337997Ssaidi@eecs.umich.edu#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 5347997Ssaidi@eecs.umich.edu#define MAF_V_DREAD_PENDING 6 5357997Ssaidi@eecs.umich.edu#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 5367997Ssaidi@eecs.umich.edu 5377997Ssaidi@eecs.umich.edu/* 5387997Ssaidi@eecs.umich.edu** 5397997Ssaidi@eecs.umich.edu** Cbox IPR Definitions: 5407997Ssaidi@eecs.umich.edu** 5417997Ssaidi@eecs.umich.edu*/ 5427997Ssaidi@eecs.umich.edu 5437997Ssaidi@eecs.umich.edu#define scCtl 0x0A8 /* RW - Scache Control */ 5447997Ssaidi@eecs.umich.edu#define scStat 0x0E8 /* RO - Scache Error Status */ 5457997Ssaidi@eecs.umich.edu#define scAddr 0x188 /* RO - Scache Error Address */ 5467997Ssaidi@eecs.umich.edu#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 5477997Ssaidi@eecs.umich.edu#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 5487997Ssaidi@eecs.umich.edu#define bcTagAddr 0x108 /* RO - Bcache Tag */ 5497997Ssaidi@eecs.umich.edu#define eiStat 0x168 /* RO - Bcache/System Error Status */ 5507997Ssaidi@eecs.umich.edu#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 5517997Ssaidi@eecs.umich.edu#define fillSyn 0x068 /* RO - Fill Syndrome */ 5527997Ssaidi@eecs.umich.edu#define ldLock 0x1E8 /* RO - LDx_L Address */ 5537997Ssaidi@eecs.umich.edu 5547997Ssaidi@eecs.umich.edu/* 5557997Ssaidi@eecs.umich.edu** 5567997Ssaidi@eecs.umich.edu** Scache Control Register (SC_CTL) Bit Summary 5577997Ssaidi@eecs.umich.edu** 5587997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5597997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5607997Ssaidi@eecs.umich.edu** <15:13> 3 SET_EN RW,1 Set enable 5617997Ssaidi@eecs.umich.edu** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 5627997Ssaidi@eecs.umich.edu** <11:08> 4 FB_DP RW,0 Force bad data parity 5637997Ssaidi@eecs.umich.edu** <07:02> 6 TAG_STAT RW Tag status and parity 5647997Ssaidi@eecs.umich.edu** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 5657997Ssaidi@eecs.umich.edu** <0> 1 FHIT RW,0 Force hits 5667997Ssaidi@eecs.umich.edu** 5677997Ssaidi@eecs.umich.edu*/ 5687997Ssaidi@eecs.umich.edu 5697997Ssaidi@eecs.umich.edu#define SC_V_SET_EN 13 5707997Ssaidi@eecs.umich.edu#define SC_M_SET_EN (7<<SC_V_SET_EN) 5717997Ssaidi@eecs.umich.edu#define SC_V_BLK_SIZE 12 5727997Ssaidi@eecs.umich.edu#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 5737997Ssaidi@eecs.umich.edu#define SC_V_FB_DP 8 5747997Ssaidi@eecs.umich.edu#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 5757997Ssaidi@eecs.umich.edu#define SC_V_TAG_STAT 2 5767997Ssaidi@eecs.umich.edu#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 5777997Ssaidi@eecs.umich.edu#define SC_V_FLUSH 1 5787997Ssaidi@eecs.umich.edu#define SC_M_FLUSH (1<<SC_V_FLUSH) 5797997Ssaidi@eecs.umich.edu#define SC_V_FHIT 0 5807997Ssaidi@eecs.umich.edu#define SC_M_FHIT (1<<SC_V_FHIT) 5817997Ssaidi@eecs.umich.edu 5827997Ssaidi@eecs.umich.edu/* 5837997Ssaidi@eecs.umich.edu** 5847997Ssaidi@eecs.umich.edu** Bcache Control Register (BC_CTL) Bit Summary 5857997Ssaidi@eecs.umich.edu** 5867997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5877997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5887997Ssaidi@eecs.umich.edu** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 5897997Ssaidi@eecs.umich.edu** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 5907997Ssaidi@eecs.umich.edu** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 5917997Ssaidi@eecs.umich.edu** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 5927997Ssaidi@eecs.umich.edu** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 5937997Ssaidi@eecs.umich.edu** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 5947997Ssaidi@eecs.umich.edu** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 5957997Ssaidi@eecs.umich.edu** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 5967997Ssaidi@eecs.umich.edu** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 5977997Ssaidi@eecs.umich.edu** <7> 1 BC_FHIT WO,0 Bcache force hit 5987997Ssaidi@eecs.umich.edu** <6> 1 EI_ECC WO,1 ECC or byte parity mode 5997997Ssaidi@eecs.umich.edu** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 6007997Ssaidi@eecs.umich.edu** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 6017997Ssaidi@eecs.umich.edu** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 6027997Ssaidi@eecs.umich.edu** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 6037997Ssaidi@eecs.umich.edu** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 6047997Ssaidi@eecs.umich.edu** <0> 1 BC_ENA W0,0 Bcache enable 6057997Ssaidi@eecs.umich.edu** 6067997Ssaidi@eecs.umich.edu*/ 6077997Ssaidi@eecs.umich.edu#define BC_V_DIS_SC_VIC_BUF 27 6087997Ssaidi@eecs.umich.edu#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 6097997Ssaidi@eecs.umich.edu#define BC_V_DIS_BAF_BYP 26 6107997Ssaidi@eecs.umich.edu#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 6117997Ssaidi@eecs.umich.edu#define BC_V_DBG_MUX_SEL 25 6127997Ssaidi@eecs.umich.edu#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 6137997Ssaidi@eecs.umich.edu#define BC_V_PM_MUX_SEL 19 6147997Ssaidi@eecs.umich.edu#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 6157997Ssaidi@eecs.umich.edu#define BC_V_BC_WAVE 17 6167997Ssaidi@eecs.umich.edu#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 6177997Ssaidi@eecs.umich.edu#define BC_V_TL_PIPE_LATCH 16 6187997Ssaidi@eecs.umich.edu#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 6197997Ssaidi@eecs.umich.edu#define BC_V_EI_DIS_ERR 15 6207997Ssaidi@eecs.umich.edu#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 6217997Ssaidi@eecs.umich.edu#define BC_V_BC_BAD_DAT 13 6227997Ssaidi@eecs.umich.edu#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 6237997Ssaidi@eecs.umich.edu#define BC_V_BC_TAG_STAT 8 6247997Ssaidi@eecs.umich.edu#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 6257997Ssaidi@eecs.umich.edu#define BC_V_BC_FHIT 7 6267997Ssaidi@eecs.umich.edu#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 6277997Ssaidi@eecs.umich.edu#define BC_V_EI_ECC_OR_PARITY 6 6287997Ssaidi@eecs.umich.edu#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 6297997Ssaidi@eecs.umich.edu#define BC_V_VTM_FIRST 5 6307997Ssaidi@eecs.umich.edu#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 6317997Ssaidi@eecs.umich.edu#define BC_V_CORR_FILL_DAT 4 6327997Ssaidi@eecs.umich.edu#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 6337997Ssaidi@eecs.umich.edu#define BC_V_EI_CMD_GRP3 3 6347997Ssaidi@eecs.umich.edu#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 6357997Ssaidi@eecs.umich.edu#define BC_V_EI_CMD_GRP2 2 6367997Ssaidi@eecs.umich.edu#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 6377997Ssaidi@eecs.umich.edu#define BC_V_ALLOC_CYC 1 6387997Ssaidi@eecs.umich.edu#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 6397997Ssaidi@eecs.umich.edu#define BC_V_BC_ENA 0 6407997Ssaidi@eecs.umich.edu#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 6417997Ssaidi@eecs.umich.edu 6427997Ssaidi@eecs.umich.edu#define BC_K_DFAULT \ 6437997Ssaidi@eecs.umich.edu (((BC_M_EI_DIS_ERR) | \ 6447997Ssaidi@eecs.umich.edu (BC_M_EI_ECC_OR_PARITY) | \ 6457997Ssaidi@eecs.umich.edu (BC_M_VTM_FIRST) | \ 6467997Ssaidi@eecs.umich.edu (BC_M_CORR_FILL_DAT))>>1) 6477997Ssaidi@eecs.umich.edu/* 6487997Ssaidi@eecs.umich.edu** 6497997Ssaidi@eecs.umich.edu** Bcache Configuration Register (BC_CONFIG) Bit Summary 6507997Ssaidi@eecs.umich.edu** 6517997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 6527997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 6537997Ssaidi@eecs.umich.edu** <35:29> 7 RSVD WO Reserved - Must Be Zero 6547997Ssaidi@eecs.umich.edu** <28:20> 9 WE_CTL WO,0 Bcache write enable control 6557997Ssaidi@eecs.umich.edu** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 6567997Ssaidi@eecs.umich.edu** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 6577997Ssaidi@eecs.umich.edu** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 6587997Ssaidi@eecs.umich.edu** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 6597997Ssaidi@eecs.umich.edu** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 6607997Ssaidi@eecs.umich.edu** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 6617997Ssaidi@eecs.umich.edu** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 6627997Ssaidi@eecs.umich.edu** <02:00> 3 SIZE WO,1 Bcache size 6637997Ssaidi@eecs.umich.edu*/ 6647997Ssaidi@eecs.umich.edu#define BC_V_WE_CTL 20 6657997Ssaidi@eecs.umich.edu#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 6667997Ssaidi@eecs.umich.edu#define BC_V_WE_OFF 16 6677997Ssaidi@eecs.umich.edu#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 6687997Ssaidi@eecs.umich.edu#define BC_V_RD_WR_SPC 12 6697997Ssaidi@eecs.umich.edu#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 6707997Ssaidi@eecs.umich.edu#define BC_V_WR_SPD 8 6717997Ssaidi@eecs.umich.edu#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 6727997Ssaidi@eecs.umich.edu#define BC_V_RD_SPD 4 6737997Ssaidi@eecs.umich.edu#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 6747997Ssaidi@eecs.umich.edu#define BC_V_SIZE 0 6757997Ssaidi@eecs.umich.edu#define BC_M_SIZE (0x7<<BC_V_SIZE) 6767997Ssaidi@eecs.umich.edu 6777997Ssaidi@eecs.umich.edu#define BC_K_CONFIG \ 6787997Ssaidi@eecs.umich.edu ((0x1<<BC_V_WE_OFF) | \ 6797997Ssaidi@eecs.umich.edu (0x7<<BC_V_RD_WR_SPC) | \ 6807997Ssaidi@eecs.umich.edu (0x4<<BC_V_WR_SPD) | \ 6817997Ssaidi@eecs.umich.edu (0x4<<BC_V_RD_SPD) | \ 6827997Ssaidi@eecs.umich.edu (0x1<<BC_V_SIZE)) 6837997Ssaidi@eecs.umich.edu 6847997Ssaidi@eecs.umich.edu/* 6857997Ssaidi@eecs.umich.edu** 6867997Ssaidi@eecs.umich.edu** DECchip 21164 Privileged Architecture Library Entry Offsets: 6877997Ssaidi@eecs.umich.edu** 6887997Ssaidi@eecs.umich.edu** Entry Name Offset (Hex) 6897997Ssaidi@eecs.umich.edu** 6907997Ssaidi@eecs.umich.edu** RESET 0000 6917997Ssaidi@eecs.umich.edu** IACCVIO 0080 6927997Ssaidi@eecs.umich.edu** INTERRUPT 0100 6937997Ssaidi@eecs.umich.edu** ITB_MISS 0180 6947997Ssaidi@eecs.umich.edu** DTB_MISS (Single) 0200 6957997Ssaidi@eecs.umich.edu** DTB_MISS (Double) 0280 6967997Ssaidi@eecs.umich.edu** UNALIGN 0300 6977997Ssaidi@eecs.umich.edu** D_FAULT 0380 6987997Ssaidi@eecs.umich.edu** MCHK 0400 6997997Ssaidi@eecs.umich.edu** OPCDEC 0480 7007997Ssaidi@eecs.umich.edu** ARITH 0500 7017997Ssaidi@eecs.umich.edu** FEN 0580 7027997Ssaidi@eecs.umich.edu** CALL_PAL (Privileged) 2000 7037997Ssaidi@eecs.umich.edu** CALL_PAL (Unprivileged) 3000 7047997Ssaidi@eecs.umich.edu** 7057997Ssaidi@eecs.umich.edu*/ 7067997Ssaidi@eecs.umich.edu 7077997Ssaidi@eecs.umich.edu#define PAL_RESET_ENTRY 0x0000 7087997Ssaidi@eecs.umich.edu#define PAL_IACCVIO_ENTRY 0x0080 7097997Ssaidi@eecs.umich.edu#define PAL_INTERRUPT_ENTRY 0x0100 7107997Ssaidi@eecs.umich.edu#define PAL_ITB_MISS_ENTRY 0x0180 7117997Ssaidi@eecs.umich.edu#define PAL_DTB_MISS_ENTRY 0x0200 7127997Ssaidi@eecs.umich.edu#define PAL_DOUBLE_MISS_ENTRY 0x0280 7137997Ssaidi@eecs.umich.edu#define PAL_UNALIGN_ENTRY 0x0300 7147997Ssaidi@eecs.umich.edu#define PAL_D_FAULT_ENTRY 0x0380 7157997Ssaidi@eecs.umich.edu#define PAL_MCHK_ENTRY 0x0400 7167997Ssaidi@eecs.umich.edu#define PAL_OPCDEC_ENTRY 0x0480 7177997Ssaidi@eecs.umich.edu#define PAL_ARITH_ENTRY 0x0500 7187997Ssaidi@eecs.umich.edu#define PAL_FEN_ENTRY 0x0580 7197997Ssaidi@eecs.umich.edu#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 7207997Ssaidi@eecs.umich.edu#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 7217997Ssaidi@eecs.umich.edu 7227997Ssaidi@eecs.umich.edu/* 7237997Ssaidi@eecs.umich.edu** 7247997Ssaidi@eecs.umich.edu** Architecturally Reserved Opcode (PALRES) Definitions: 7257997Ssaidi@eecs.umich.edu** 7267997Ssaidi@eecs.umich.edu*/ 7277997Ssaidi@eecs.umich.edu 7287997Ssaidi@eecs.umich.edu#define mtpr hw_mtpr 7297997Ssaidi@eecs.umich.edu#define mfpr hw_mfpr 7307997Ssaidi@eecs.umich.edu 7317997Ssaidi@eecs.umich.edu#define ldl_a hw_ldl/a 7327997Ssaidi@eecs.umich.edu#define ldq_a hw_ldq/a 7337997Ssaidi@eecs.umich.edu#define stq_a hw_stq/a 7347997Ssaidi@eecs.umich.edu#define stl_a hw_stl/a 7357997Ssaidi@eecs.umich.edu 7367997Ssaidi@eecs.umich.edu#define ldl_p hw_ldl/p 7377997Ssaidi@eecs.umich.edu#define ldq_p hw_ldq/p 7387997Ssaidi@eecs.umich.edu#define stl_p hw_stl/p 7397997Ssaidi@eecs.umich.edu#define stq_p hw_stq/p 7407997Ssaidi@eecs.umich.edu 7417997Ssaidi@eecs.umich.edu/* 7427997Ssaidi@eecs.umich.edu** Virtual PTE fetch variants of HW_LD. 7437997Ssaidi@eecs.umich.edu*/ 7447997Ssaidi@eecs.umich.edu#define ld_vpte hw_ldq/v 7457997Ssaidi@eecs.umich.edu 7467997Ssaidi@eecs.umich.edu/* 7477997Ssaidi@eecs.umich.edu** Physical mode load-lock and store-conditional variants of 7487997Ssaidi@eecs.umich.edu** HW_LD and HW_ST. 7497997Ssaidi@eecs.umich.edu*/ 7507997Ssaidi@eecs.umich.edu 7517997Ssaidi@eecs.umich.edu#define ldq_lp hw_ldq/pl 7527997Ssaidi@eecs.umich.edu#define stq_cp hw_stq/pc 7537997Ssaidi@eecs.umich.edu 7547997Ssaidi@eecs.umich.edu/* 7557997Ssaidi@eecs.umich.edu** 7567997Ssaidi@eecs.umich.edu** General Purpose Register Definitions: 7577997Ssaidi@eecs.umich.edu** 7587997Ssaidi@eecs.umich.edu*/ 7597997Ssaidi@eecs.umich.edu 7607997Ssaidi@eecs.umich.edu#define r0 $0 7617997Ssaidi@eecs.umich.edu#define r1 $1 7627997Ssaidi@eecs.umich.edu#define r2 $2 7637997Ssaidi@eecs.umich.edu#define r3 $3 7647997Ssaidi@eecs.umich.edu#define r4 $4 7657997Ssaidi@eecs.umich.edu#define r5 $5 7667997Ssaidi@eecs.umich.edu#define r6 $6 7677997Ssaidi@eecs.umich.edu#define r7 $7 7687997Ssaidi@eecs.umich.edu#define r8 $8 7697997Ssaidi@eecs.umich.edu#define r9 $9 7707997Ssaidi@eecs.umich.edu#define r10 $10 7717997Ssaidi@eecs.umich.edu#define r11 $11 7727997Ssaidi@eecs.umich.edu#define r12 $12 7737997Ssaidi@eecs.umich.edu#define r13 $13 7747997Ssaidi@eecs.umich.edu#define r14 $14 7757997Ssaidi@eecs.umich.edu#define r15 $15 7767997Ssaidi@eecs.umich.edu#define r16 $16 7777997Ssaidi@eecs.umich.edu#define r17 $17 7787997Ssaidi@eecs.umich.edu#define r18 $18 7797997Ssaidi@eecs.umich.edu#define r19 $19 7807997Ssaidi@eecs.umich.edu#define r20 $20 7817997Ssaidi@eecs.umich.edu#define r21 $21 7827997Ssaidi@eecs.umich.edu#define r22 $22 7837997Ssaidi@eecs.umich.edu#define r23 $23 7847997Ssaidi@eecs.umich.edu#define r24 $24 7857997Ssaidi@eecs.umich.edu#define r25 $25 7867997Ssaidi@eecs.umich.edu#define r26 $26 7877997Ssaidi@eecs.umich.edu#define r27 $27 7887997Ssaidi@eecs.umich.edu#define r28 $28 7897997Ssaidi@eecs.umich.edu#define r29 $29 7907997Ssaidi@eecs.umich.edu#define r30 $30 7917997Ssaidi@eecs.umich.edu#define r31 $31 7927997Ssaidi@eecs.umich.edu 7937997Ssaidi@eecs.umich.edu/* 7947997Ssaidi@eecs.umich.edu** 7957997Ssaidi@eecs.umich.edu** Floating Point Register Definitions: 7967997Ssaidi@eecs.umich.edu** 7977997Ssaidi@eecs.umich.edu*/ 7987997Ssaidi@eecs.umich.edu 7997997Ssaidi@eecs.umich.edu#define f0 $f0 8007997Ssaidi@eecs.umich.edu#define f1 $f1 8017997Ssaidi@eecs.umich.edu#define f2 $f2 8027997Ssaidi@eecs.umich.edu#define f3 $f3 8037997Ssaidi@eecs.umich.edu#define f4 $f4 8047997Ssaidi@eecs.umich.edu#define f5 $f5 8057997Ssaidi@eecs.umich.edu#define f6 $f6 8067997Ssaidi@eecs.umich.edu#define f7 $f7 8077997Ssaidi@eecs.umich.edu#define f8 $f8 8087997Ssaidi@eecs.umich.edu#define f9 $f9 8097997Ssaidi@eecs.umich.edu#define f10 $f10 8107997Ssaidi@eecs.umich.edu#define f11 $f11 8117997Ssaidi@eecs.umich.edu#define f12 $f12 8127997Ssaidi@eecs.umich.edu#define f13 $f13 8137997Ssaidi@eecs.umich.edu#define f14 $f14 8147997Ssaidi@eecs.umich.edu#define f15 $f15 8157997Ssaidi@eecs.umich.edu#define f16 $f16 8167997Ssaidi@eecs.umich.edu#define f17 $f17 8177997Ssaidi@eecs.umich.edu#define f18 $f18 8187997Ssaidi@eecs.umich.edu#define f19 $f19 8197997Ssaidi@eecs.umich.edu#define f20 $f20 8207997Ssaidi@eecs.umich.edu#define f21 $f21 8217997Ssaidi@eecs.umich.edu#define f22 $f22 8227997Ssaidi@eecs.umich.edu#define f23 $f23 8237997Ssaidi@eecs.umich.edu#define f24 $f24 8247997Ssaidi@eecs.umich.edu#define f25 $f25 8257997Ssaidi@eecs.umich.edu#define f26 $f26 8267997Ssaidi@eecs.umich.edu#define f27 $f27 8277997Ssaidi@eecs.umich.edu#define f28 $f28 8287997Ssaidi@eecs.umich.edu#define f29 $f29 8297997Ssaidi@eecs.umich.edu#define f30 $f30 8307997Ssaidi@eecs.umich.edu#define f31 $f31 8317997Ssaidi@eecs.umich.edu 8327997Ssaidi@eecs.umich.edu/* 8337997Ssaidi@eecs.umich.edu** 8347997Ssaidi@eecs.umich.edu** PAL Temporary Register Definitions: 8357997Ssaidi@eecs.umich.edu** 8367997Ssaidi@eecs.umich.edu*/ 8377997Ssaidi@eecs.umich.edu 8387997Ssaidi@eecs.umich.edu// covered by fetch distribution..pb Nov/95 8397997Ssaidi@eecs.umich.edu 8407997Ssaidi@eecs.umich.edu// #define pt0 0x140 8417997Ssaidi@eecs.umich.edu// #define pt1 0x141 8427997Ssaidi@eecs.umich.edu// #define pt2 0x142 8437997Ssaidi@eecs.umich.edu// #define pt3 0x143 8447997Ssaidi@eecs.umich.edu// #define pt4 0x144 8457997Ssaidi@eecs.umich.edu// #define pt5 0x145 8467997Ssaidi@eecs.umich.edu// #define pt6 0x146 8477997Ssaidi@eecs.umich.edu// #define pt7 0x147 8487997Ssaidi@eecs.umich.edu// #define pt8 0x148 8497997Ssaidi@eecs.umich.edu// #define pt9 0x149 8507997Ssaidi@eecs.umich.edu// #define pt10 0x14A 8517997Ssaidi@eecs.umich.edu// #define pt11 0x14B 8527997Ssaidi@eecs.umich.edu// #define pt12 0x14C 8537997Ssaidi@eecs.umich.edu// #define pt13 0x14D 8547997Ssaidi@eecs.umich.edu// #define pt14 0x14E 8557997Ssaidi@eecs.umich.edu// #define pt15 0x14F 8567997Ssaidi@eecs.umich.edu// #define pt16 0x150 8577997Ssaidi@eecs.umich.edu// #define pt17 0x151 8587997Ssaidi@eecs.umich.edu// #define pt18 0x152 8597997Ssaidi@eecs.umich.edu// #define pt19 0x153 8607997Ssaidi@eecs.umich.edu// #define pt20 0x154 8617997Ssaidi@eecs.umich.edu// #define pt21 0x155 8627997Ssaidi@eecs.umich.edu// #define pt22 0x156 8637997Ssaidi@eecs.umich.edu// #define pt23 0x157 8647997Ssaidi@eecs.umich.edu 8657997Ssaidi@eecs.umich.edu/* 8667997Ssaidi@eecs.umich.edu** PAL Shadow Registers: 8677997Ssaidi@eecs.umich.edu** 8687997Ssaidi@eecs.umich.edu** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 8697997Ssaidi@eecs.umich.edu** ICSR<SDE> = 1. 8707997Ssaidi@eecs.umich.edu*/ 8717997Ssaidi@eecs.umich.edu 8727997Ssaidi@eecs.umich.edu#define p0 r8 /* ITB/DTB Miss Scratch */ 8737997Ssaidi@eecs.umich.edu#define p1 r9 /* ITB/DTB Miss Scratch */ 8747997Ssaidi@eecs.umich.edu#define p2 r10 /* ITB/DTB Miss Scratch */ 8757997Ssaidi@eecs.umich.edu#define p3 r11 8767997Ssaidi@eecs.umich.edu// #define ps r11 /* Processor Status */ 8777997Ssaidi@eecs.umich.edu#define p4 r12 /* Local Scratch */ 8787997Ssaidi@eecs.umich.edu#define p5 r13 /* Local Scratch */ 8797997Ssaidi@eecs.umich.edu#define p6 r14 /* Local Scratch */ 8807997Ssaidi@eecs.umich.edu#define p7 r25 /* Local Scratch */ 8817997Ssaidi@eecs.umich.edu 8827997Ssaidi@eecs.umich.edu/* 8837997Ssaidi@eecs.umich.edu** SRM Defined State Definitions: 8847997Ssaidi@eecs.umich.edu*/ 8857997Ssaidi@eecs.umich.edu 8867997Ssaidi@eecs.umich.edu/* 8877997Ssaidi@eecs.umich.edu** This table is an accounting of the DECchip 21164 storage used to 8887997Ssaidi@eecs.umich.edu** implement the SRM defined state for OSF/1. 8897997Ssaidi@eecs.umich.edu** 8907997Ssaidi@eecs.umich.edu** IPR Name Internal Storage 8917997Ssaidi@eecs.umich.edu** -------- ---------------- 8927997Ssaidi@eecs.umich.edu** Processor Status ps, dtbCm, ipl, r11 8937997Ssaidi@eecs.umich.edu** Program Counter Ibox 8947997Ssaidi@eecs.umich.edu** Interrupt Entry ptEntInt 8957997Ssaidi@eecs.umich.edu** Arith Trap Entry ptEntArith 8967997Ssaidi@eecs.umich.edu** MM Fault Entry ptEntMM 8977997Ssaidi@eecs.umich.edu** Unaligned Access Entry ptEntUna 8987997Ssaidi@eecs.umich.edu** Instruction Fault Entry ptEntIF 8997997Ssaidi@eecs.umich.edu** Call System Entry ptEntSys 9007997Ssaidi@eecs.umich.edu** User Stack Pointer ptUsp 9017997Ssaidi@eecs.umich.edu** Kernel Stack Pointer ptKsp 9027997Ssaidi@eecs.umich.edu** Kernel Global Pointer ptKgp 9037997Ssaidi@eecs.umich.edu** System Value ptSysVal 9047997Ssaidi@eecs.umich.edu** Page Table Base Register ptPtbr 9057997Ssaidi@eecs.umich.edu** Virtual Page Table Base iVptBr, mVptBr 9067997Ssaidi@eecs.umich.edu** Process Control Block Base ptPcbb 9077997Ssaidi@eecs.umich.edu** Address Space Number itbAsn, dtbAsn 9087997Ssaidi@eecs.umich.edu** Cycle Counter cc, ccCtl 9097997Ssaidi@eecs.umich.edu** Float Point Enable icsr 9107997Ssaidi@eecs.umich.edu** Lock Flag Cbox/System 9117997Ssaidi@eecs.umich.edu** Unique PCB 9127997Ssaidi@eecs.umich.edu** Who-Am-I ptWhami 9137997Ssaidi@eecs.umich.edu*/ 9147997Ssaidi@eecs.umich.edu 9157997Ssaidi@eecs.umich.edu#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 9167997Ssaidi@eecs.umich.edu#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 9177997Ssaidi@eecs.umich.edu#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 9187997Ssaidi@eecs.umich.edu#define ptIntMask pt8 /* Interrupt Enable Mask */ 9197997Ssaidi@eecs.umich.edu#define ptEntSys pt9 /* Call System Dispatch Entry */ 9207997Ssaidi@eecs.umich.edu#define ptTrap pt11 9217997Ssaidi@eecs.umich.edu#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 9227997Ssaidi@eecs.umich.edu#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 9237997Ssaidi@eecs.umich.edu#if defined(KDEBUG) 9247997Ssaidi@eecs.umich.edu#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 9257997Ssaidi@eecs.umich.edu#endif /* KDEBUG */ 9267997Ssaidi@eecs.umich.edu#define ptMisc pt16 /* Miscellaneous Flags */ 9277997Ssaidi@eecs.umich.edu#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 9287997Ssaidi@eecs.umich.edu#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 9297997Ssaidi@eecs.umich.edu#define ptSysVal pt17 /* Per-Processor System Value */ 9307997Ssaidi@eecs.umich.edu#define ptUsp pt18 /* User Stack Pointer */ 9317997Ssaidi@eecs.umich.edu#define ptKsp pt19 /* Kernel Stack Pointer */ 9327997Ssaidi@eecs.umich.edu#define ptPtbr pt20 /* Page Table Base Register */ 9337997Ssaidi@eecs.umich.edu#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 9347997Ssaidi@eecs.umich.edu#define ptKgp pt22 /* Kernel Global Pointer */ 9357997Ssaidi@eecs.umich.edu#define ptPcbb pt23 /* Process Control Block Base */ 9367997Ssaidi@eecs.umich.edu 9377997Ssaidi@eecs.umich.edu/* 9387997Ssaidi@eecs.umich.edu** 9397997Ssaidi@eecs.umich.edu** Miscellaneous PAL State Flags (ptMisc) Bit Summary 9407997Ssaidi@eecs.umich.edu** 9417997Ssaidi@eecs.umich.edu** Extent Size Name Function 9427997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 9437997Ssaidi@eecs.umich.edu** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 9447997Ssaidi@eecs.umich.edu** <47:32> 16 MCHK Machine Check Error code 9457997Ssaidi@eecs.umich.edu** <31:16> 16 SCB System Control Block vector 9467997Ssaidi@eecs.umich.edu** <15:08> 8 WHAMI Who-Am-I identifier 9477997Ssaidi@eecs.umich.edu** <04:00> 5 MCES Machine Check Error Summary bits 9487997Ssaidi@eecs.umich.edu** 9497997Ssaidi@eecs.umich.edu*/ 9507997Ssaidi@eecs.umich.edu 9517997Ssaidi@eecs.umich.edu#define PT16_V_MCES 0 9527997Ssaidi@eecs.umich.edu#define PT16_V_WHAMI 8 9537997Ssaidi@eecs.umich.edu#define PT16_V_SCB 16 9547997Ssaidi@eecs.umich.edu#define PT16_V_MCHK 32 9557997Ssaidi@eecs.umich.edu#define PT16_V_SWAP 48 9567997Ssaidi@eecs.umich.edu 9577997Ssaidi@eecs.umich.edu#endif /* DC21164FROMGASSOURCES_INCLUDED */ 958