dc21164FromGasSources.h revision 8012
1/* 2Copyright 1993 Hewlett-Packard Development Company, L.P. 3 4Permission is hereby granted, free of charge, to any person obtaining a copy of 5this software and associated documentation files (the "Software"), to deal in 6the Software without restriction, including without limitation the rights to 7use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 8of the Software, and to permit persons to whom the Software is furnished to do 9so, subject to the following conditions: 10 11The above copyright notice and this permission notice shall be included in all 12copies or substantial portions of the Software. 13 14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20SOFTWARE. 21*/ 22 23#ifndef DC21164FROMGASSOURCES_INCLUDED 24#define DC21164FROMGASSOURCES_INCLUDED 1 25 26/* 27** 28** FACILITY: 29** 30** DECchip 21164 PALcode 31** 32** MODULE: 33** 34** dc21164.h 35** 36** MODULE DESCRIPTION: 37** 38** DECchip 21164 specific definitions 39** 40** AUTHOR: ER 41** 42** CREATION DATE: 24-Nov-1993 43** 44** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 45** 46** MODIFICATION HISTORY: 47** 48** $Log: dc21164FromGasSources.h,v $ 49** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 50** current 10/29/97 51** 52** Revision 1.1 1995/11/18 01:45:46 boyle 53** Initial revision 54** 55** Revision 1.15 1995/04/21 02:06:30 fdh 56** Replaced C++ style comments with Standard C style comments. 57** 58** Revision 1.14 1995/03/20 14:55:23 samberg 59** Add flushIc to make Roger Cruz's life easier. 60** 61** Revision 1.13 1994/12/14 15:52:48 samberg 62** Add slXmit and slRcv bit definitions 63** 64** Revision 1.12 1994/09/07 15:43:49 samberg 65** Changes for Makefile.vpp, take out OSF definition 66** 67** Revision 1.11 1994/07/26 17:38:35 samberg 68** Changes for SD164. 69** 70** Revision 1.10 1994/07/08 17:02:12 samberg 71** Changes to support platform specific additions 72** 73** Revision 1.8 1994/05/31 15:49:21 ericr 74** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows 75** 76** Revision 1.7 1994/05/26 19:29:51 ericr 77** Added BC_CONFIG definitions 78** 79** Revision 1.6 1994/05/25 14:27:25 ericr 80** Added physical bit to ldq_lp and stq_cp macros 81** 82** Revision 1.5 1994/05/20 18:07:50 ericr 83** Changed line comments to C++ style comment character 84** 85** Revision 1.4 1994/01/17 21:46:54 ericr 86** Added floating point register definitions 87** 88** Revision 1.3 1994/01/03 19:31:49 ericr 89** Added cache parity error status register definitions 90** 91** Revision 1.2 1993/12/22 20:42:35 eric 92** Added ptTrap, ptMisc and flag definitions 93** Added PAL shadow regsiter definitions 94** 95** Revision 1.1 1993/12/16 21:55:05 eric 96** Initial revision 97** 98** 99**-- 100*/ 101 102 103/* 104** 105** INTERNAL PROCESSOR REGISTER DEFINITIONS 106** 107** The internal processor register definitions below are annotated 108** with one of the following symbols: 109** 110** RW - The register may be read and written 111** RO - The register may only be read 112** WO - The register may only be written 113** 114** For RO and WO registers, all bits and fields within the register are 115** also read-only or write-only. For RW registers, each bit or field 116** within the register is annotated with one of the following: 117** 118** RW - The bit/field may be read and written 119** RO - The bit/field may be read; writes are ignored 120** WO - The bit/field may be written; reads return UNPREDICTABLE 121** WZ - The bit/field may be written; reads return a zero value 122** W0C - The bit/field may be read; write-zero-to-clear 123** W1C - The bit/field may be read; write-one-to-clear 124** WA - The bit/field may be read; write-anything-to-clear 125** RC - The bit/field may be read, causing state to clear; 126** writes are ignored 127** 128*/ 129 130 131/* 132** 133** Ibox IPR Definitions: 134** 135*/ 136 137// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 138#define itbTag 0x101 /* WO - ITB Tag */ 139#define itbPte 0x102 /* RW - ITB Page Table Entry */ 140#define itbAsn 0x103 /* RW - ITB Address Space Number */ 141#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 142#define itbIa 0x105 /* WO - ITB Invalidate All */ 143#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 144#define itbIs 0x107 /* WO - ITB Invalidate Single */ 145// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 146// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 147// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 148#define excAddr 0x10B /* RW - Exception Address */ 149#define excSum 0x10C /* RW - Exception Summary */ 150#define excMask 0x10D /* RO - Exception Mask */ 151#define palBase 0x10E /* RW - PAL Base */ 152#define ips 0x10F /* RW - Processor Status */ 153// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 154#define intId 0x111 /* RO - Interrupt ID */ 155#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 156#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 157#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 158#define slXmit 0x116 /* WO - Serial Line Transmit */ 159#define slRcv 0x117 /* RO - Serial Line Receive */ 160// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 161#define icFlush 0x119 /* WO - I-Cache Flush Control */ 162#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 163#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 164#define PmCtr 0x11C /* RW - Performance Counter */ 165 166/* 167** 168** Ibox Control/Status Register (ICSR) Bit Summary 169** 170** Extent Size Name Type Function 171** ------ ---- ---- ---- ------------------------------------ 172** <39> 1 TST RW,0 Assert Test Status 173** <38> 1 ISTA RO I-Cache BIST Status 174** <37> 1 DBS RW,1 Debug Port Select 175** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 176** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 177** <34> 1 FMS RW,0 Force I-Cache Miss 178** <33> 1 SLE RW,0 Enable Serial Line Interrupts 179** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 180** <30> 1 SDE RW,0 Enable PAL Shadow Registers 181** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 182** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 183** <26> 1 FPE RW,0 Enable Floating Point Instructions 184** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 185** <24> 1 TMM RW,0 Timeout Counter Mode 186** 187*/ 188 189#define ICSR_V_TST 39 190#define ICSR_M_TST (1<<ICSR_V_TST) 191#define ICSR_V_ISTA 38 192#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 193#define ICSR_V_DBS 37 194#define ICSR_M_DBS (1<<ICSR_V_DBS) 195#define ICSR_V_FBD 36 196#define ICSR_M_FBD (1<<ICSR_V_FBD) 197#define ICSR_V_FBT 35 198#define ICSR_M_FBT (1<<ICSR_V_FBT) 199#define ICSR_V_FMS 34 200#define ICSR_M_FMS (1<<ICSR_V_FMS) 201#define ICSR_V_SLE 33 202#define ICSR_M_SLE (1<<ICSR_V_SLE) 203#define ICSR_V_CRDE 32 204#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 205#define ICSR_V_SDE 30 206#define ICSR_M_SDE (1<<ICSR_V_SDE) 207#define ICSR_V_SPE 28 208#define ICSR_M_SPE (3<<ICSR_V_SPE) 209#define ICSR_V_HWE 27 210#define ICSR_M_HWE (1<<ICSR_V_HWE) 211#define ICSR_V_FPE 26 212#define ICSR_M_FPE (1<<ICSR_V_FPE) 213#define ICSR_V_TMD 25 214#define ICSR_M_TMD (1<<ICSR_V_TMD) 215#define ICSR_V_TMM 24 216#define ICSR_M_TMM (1<<ICSR_V_TMM) 217 218/* 219** 220** Serial Line Tranmit Register (SL_XMIT) 221** 222** Extent Size Name Type Function 223** ------ ---- ---- ---- ------------------------------------ 224** <7> 1 TMT WO,1 Serial line transmit data 225** 226*/ 227 228#define SLXMIT_V_TMT 7 229#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 230 231/* 232** 233** Serial Line Receive Register (SL_RCV) 234** 235** Extent Size Name Type Function 236** ------ ---- ---- ---- ------------------------------------ 237** <6> 1 RCV RO Serial line receive data 238** 239*/ 240 241#define SLRCV_V_RCV 6 242#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 243 244/* 245** 246** Icache Parity Error Status Register (ICPERR) Bit Summary 247** 248** Extent Size Name Type Function 249** ------ ---- ---- ---- ------------------------------------ 250** <13> 1 TMR W1C Timeout reset error 251** <12> 1 TPE W1C Tag parity error 252** <11> 1 DPE W1C Data parity error 253** 254*/ 255 256#define ICPERR_V_TMR 13 257#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 258#define ICPERR_V_TPE 12 259#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 260#define ICPERR_V_DPE 11 261#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 262 263#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 264 265/* 266** 267** Exception Summary Register (EXC_SUM) Bit Summary 268** 269** Extent Size Name Type Function 270** ------ ---- ---- ---- ------------------------------------ 271** <16> 1 IOV WA Integer overflow 272** <15> 1 INE WA Inexact result 273** <14> 1 UNF WA Underflow 274** <13> 1 FOV WA Overflow 275** <12> 1 DZE WA Division by zero 276** <11> 1 INV WA Invalid operation 277** <10> 1 SWC WA Software completion 278** 279*/ 280 281#define EXC_V_IOV 16 282#define EXC_M_IOV (1<<EXC_V_IOV) 283#define EXC_V_INE 15 284#define EXC_M_INE (1<<EXC_V_INE) 285#define EXC_V_UNF 14 286#define EXC_M_UNF (1<<EXC_V_UNF) 287#define EXC_V_FOV 13 288#define EXC_M_FOV (1<<EXC_V_FOV) 289#define EXC_V_DZE 12 290#define EXC_M_DZE (1<<EXC_V_DZE) 291#define EXC_V_INV 11 292#define EXC_M_INV (1<<EXC_V_INV) 293#define EXC_V_SWC 10 294#define EXC_M_SWC (1<<EXC_V_SWC) 295 296/* 297** 298** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 299** 300** Extent Size Name Type Function 301** ------ ---- ---- ---- --------------------------------- 302** <33> 1 SLC W1C Clear Serial Line interrupt 303** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 304** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 305** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 306** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 307** 308*/ 309 310#define HWINT_V_SLC 33 311#define HWINT_M_SLC (1<<HWINT_V_SLC) 312#define HWINT_V_CRDC 32 313#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 314#define HWINT_V_PC2C 29 315#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 316#define HWINT_V_PC1C 28 317#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 318#define HWINT_V_PC0C 27 319#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 320 321/* 322** 323** Interrupt Summary Register (ISR) Bit Summary 324** 325** Extent Size Name Type Function 326** ------ ---- ---- ---- --------------------------------- 327** <34> 1 HLT RO External Halt interrupt 328** <33> 1 SLI RO Serial Line interrupt 329** <32> 1 CRD RO Correctable ECC errors 330** <31> 1 MCK RO System Machine Check 331** <30> 1 PFL RO Power Fail 332** <29> 1 PC2 RO Performance Counter 2 interrupt 333** <28> 1 PC1 RO Performance Counter 1 interrupt 334** <27> 1 PC0 RO Performance Counter 0 interrupt 335** <23> 1 I23 RO External Hardware interrupt 336** <22> 1 I22 RO External Hardware interrupt 337** <21> 1 I21 RO External Hardware interrupt 338** <20> 1 I20 RO External Hardware interrupt 339** <19> 1 ATR RO Async. System Trap request 340** <18:4> 15 SIRR RO,0 Software Interrupt request 341** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 342** 343**/ 344 345#define ISR_V_HLT 34 346#define ISR_M_HLT (1<<ISR_V_HLT) 347#define ISR_V_SLI 33 348#define ISR_M_SLI (1<<ISR_V_SLI) 349#define ISR_V_CRD 32 350#define ISR_M_CRD (1<<ISR_V_CRD) 351#define ISR_V_MCK 31 352#define ISR_M_MCK (1<<ISR_V_MCK) 353#define ISR_V_PFL 30 354#define ISR_M_PFL (1<<ISR_V_PFL) 355#define ISR_V_PC2 29 356#define ISR_M_PC2 (1<<ISR_V_PC2) 357#define ISR_V_PC1 28 358#define ISR_M_PC1 (1<<ISR_V_PC1) 359#define ISR_V_PC0 27 360#define ISR_M_PC0 (1<<ISR_V_PC0) 361#define ISR_V_I23 23 362#define ISR_M_I23 (1<<ISR_V_I23) 363#define ISR_V_I22 22 364#define ISR_M_I22 (1<<ISR_V_I22) 365#define ISR_V_I21 21 366#define ISR_M_I21 (1<<ISR_V_I21) 367#define ISR_V_I20 20 368#define ISR_M_I20 (1<<ISR_V_I20) 369#define ISR_V_ATR 19 370#define ISR_M_ATR (1<<ISR_V_ATR) 371#define ISR_V_SIRR 4 372#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 373#define ISR_V_ASTRR 0 374#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 375 376/* 377** 378** Mbox and D-Cache IPR Definitions: 379** 380*/ 381 382#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 383#define dtbCm 0x201 /* WO - DTB Current Mode */ 384#define dtbTag 0x202 /* WO - DTB Tag */ 385#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 386#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 387#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 388// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 389#define vaForm 0x207 /* RO - Formatted Virtual Address */ 390#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 391#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 392#define dtbIa 0x20A /* WO - DTB Invalidate All */ 393#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 394#define altMode 0x20C /* WO - Alternate Mode */ 395// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 396#define ccCtl 0x20E /* WO - Cycle Counter Control */ 397// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 398#define dcFlush 0x210 /* WO - Dcache Flush */ 399#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 400#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 401#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 402#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 403#define dcMode 0x216 /* RW - Dcache Mode */ 404#define mafMode 0x217 /* RW - Miss Address File Mode */ 405 406/* 407** 408** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 409** 410** Extent Size Name Type Function 411** ------ ---- ---- ---- --------------------------------- 412** <16:11> 6 OPCODE RO Opcode of faulting instruction 413** <10:06> 5 RA RO Ra field of faulting instruction 414** <5> 1 BAD_VA RO Bad virtual address 415** <4> 1 DTB_MISS RO Reference resulted in DTB miss 416** <3> 1 FOW RO Fault on write 417** <2> 1 FOR RO Fault on read 418** <1> 1 ACV RO Access violation 419** <0> 1 WR RO Reference type 420** 421*/ 422 423#define MMSTAT_V_OPC 11 424#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 425#define MMSTAT_V_RA 6 426#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 427#define MMSTAT_V_BAD_VA 5 428#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 429#define MMSTAT_V_DTB_MISS 4 430#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 431#define MMSTAT_V_FOW 3 432#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 433#define MMSTAT_V_FOR 2 434#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 435#define MMSTAT_V_ACV 1 436#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 437#define MMSTAT_V_WR 0 438#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 439 440 441/* 442** 443** Mbox Control Register (MCSR) Bit Summary 444** 445** Extent Size Name Type Function 446** ------ ---- ---- ---- --------------------------------- 447** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 448** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 449** <3> 1 DBG0 RW,0 Debug Test Select 450** <2:1> 2 SP RW,0 Superpage mode enable 451** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 452** 453*/ 454 455#define MCSR_V_DBG1 5 456#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 457#define MCSR_V_E_BE 4 458#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 459#define MCSR_V_DBG0 3 460#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 461#define MCSR_V_SP 1 462#define MCSR_M_SP (3<<MCSR_V_SP) 463#define MCSR_V_M_BE 0 464#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 465 466/* 467** 468** Dcache Parity Error Status Register (DCPERR) Bit Summary 469** 470** Extent Size Name Type Function 471** ------ ---- ---- ---- ------------------------------------ 472** <5> 1 TP1 RO Dcache bank 1 tag parity error 473** <4> 1 TP0 RO Dcache bank 0 tag parity error 474** <3> 1 DP1 RO Dcache bank 1 data parity error 475** <2> 1 DP0 RO Dcache bank 0 data parity error 476** <1> 1 LOCK W1C Locks/clears bits <5:2> 477** <0> 1 SEO W1C Second Dcache parity error occurred 478** 479*/ 480 481#define DCPERR_V_TP1 5 482#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 483#define DCPERR_V_TP0 4 484#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 485#define DCPERR_V_DP1 3 486#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 487#define DCPERR_V_DP0 2 488#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 489#define DCPERR_V_LOCK 1 490#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 491#define DCPERR_V_SEO 0 492#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 493 494#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 495 496/* 497** 498** Dcache Mode Register (DC_MODE) Bit Summary 499** 500** Extent Size Name Type Function 501** ------ ---- ---- ---- --------------------------------- 502** <4> 1 DOA RO Hardware Dcache Disable 503** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 504** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 505** <1> 1 FHIT RW,0 Force Dcache hit 506** <0> 1 ENA RW,0 Software Dcache Enable 507** 508*/ 509 510#define DC_V_DOA 4 511#define DC_M_DOA (1<<DC_V_DOA) 512#define DC_V_PERR_DIS 3 513#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 514#define DC_V_BAD_DP 2 515#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 516#define DC_V_FHIT 1 517#define DC_M_FHIT (1<<DC_V_FHIT) 518#define DC_V_ENA 0 519#define DC_M_ENA (1<<DC_V_ENA) 520 521/* 522** 523** Miss Address File Mode Register (MAF_MODE) Bit Summay 524** 525** Extent Size Name Type Function 526** ------ ---- ---- ---- --------------------------------- 527** <7> 1 WB RO,0 If set, pending WB request 528** <6> 1 DREAD RO,0 If set, pending D-read request 529** 530*/ 531 532#define MAF_V_WB_PENDING 7 533#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 534#define MAF_V_DREAD_PENDING 6 535#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 536 537/* 538** 539** Cbox IPR Definitions: 540** 541*/ 542 543#define scCtl 0x0A8 /* RW - Scache Control */ 544#define scStat 0x0E8 /* RO - Scache Error Status */ 545#define scAddr 0x188 /* RO - Scache Error Address */ 546#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 547#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 548#define bcTagAddr 0x108 /* RO - Bcache Tag */ 549#define eiStat 0x168 /* RO - Bcache/System Error Status */ 550#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 551#define fillSyn 0x068 /* RO - Fill Syndrome */ 552#define ldLock 0x1E8 /* RO - LDx_L Address */ 553 554/* 555** 556** Scache Control Register (SC_CTL) Bit Summary 557** 558** Extent Size Name Type Function 559** ------ ---- ---- ---- --------------------------------- 560** <15:13> 3 SET_EN RW,1 Set enable 561** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 562** <11:08> 4 FB_DP RW,0 Force bad data parity 563** <07:02> 6 TAG_STAT RW Tag status and parity 564** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 565** <0> 1 FHIT RW,0 Force hits 566** 567*/ 568 569#define SC_V_SET_EN 13 570#define SC_M_SET_EN (7<<SC_V_SET_EN) 571#define SC_V_BLK_SIZE 12 572#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 573#define SC_V_FB_DP 8 574#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 575#define SC_V_TAG_STAT 2 576#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 577#define SC_V_FLUSH 1 578#define SC_M_FLUSH (1<<SC_V_FLUSH) 579#define SC_V_FHIT 0 580#define SC_M_FHIT (1<<SC_V_FHIT) 581 582/* 583** 584** Bcache Control Register (BC_CTL) Bit Summary 585** 586** Extent Size Name Type Function 587** ------ ---- ---- ---- --------------------------------- 588** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 589** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 590** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 591** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 592** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 593** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 594** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 595** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 596** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 597** <7> 1 BC_FHIT WO,0 Bcache force hit 598** <6> 1 EI_ECC WO,1 ECC or byte parity mode 599** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 600** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 601** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 602** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 603** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 604** <0> 1 BC_ENA W0,0 Bcache enable 605** 606*/ 607#define BC_V_DIS_SC_VIC_BUF 27 608#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 609#define BC_V_DIS_BAF_BYP 26 610#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 611#define BC_V_DBG_MUX_SEL 25 612#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 613#define BC_V_PM_MUX_SEL 19 614#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 615#define BC_V_BC_WAVE 17 616#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 617#define BC_V_TL_PIPE_LATCH 16 618#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 619#define BC_V_EI_DIS_ERR 15 620#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 621#define BC_V_BC_BAD_DAT 13 622#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 623#define BC_V_BC_TAG_STAT 8 624#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 625#define BC_V_BC_FHIT 7 626#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 627#define BC_V_EI_ECC_OR_PARITY 6 628#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 629#define BC_V_VTM_FIRST 5 630#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 631#define BC_V_CORR_FILL_DAT 4 632#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 633#define BC_V_EI_CMD_GRP3 3 634#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 635#define BC_V_EI_CMD_GRP2 2 636#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 637#define BC_V_ALLOC_CYC 1 638#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 639#define BC_V_BC_ENA 0 640#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 641 642#define BC_K_DFAULT \ 643 (((BC_M_EI_DIS_ERR) | \ 644 (BC_M_EI_ECC_OR_PARITY) | \ 645 (BC_M_VTM_FIRST) | \ 646 (BC_M_CORR_FILL_DAT))>>1) 647/* 648** 649** Bcache Configuration Register (BC_CONFIG) Bit Summary 650** 651** Extent Size Name Type Function 652** ------ ---- ---- ---- --------------------------------- 653** <35:29> 7 RSVD WO Reserved - Must Be Zero 654** <28:20> 9 WE_CTL WO,0 Bcache write enable control 655** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 656** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 657** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 658** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 659** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 660** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 661** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 662** <02:00> 3 SIZE WO,1 Bcache size 663*/ 664#define BC_V_WE_CTL 20 665#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 666#define BC_V_WE_OFF 16 667#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 668#define BC_V_RD_WR_SPC 12 669#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 670#define BC_V_WR_SPD 8 671#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 672#define BC_V_RD_SPD 4 673#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 674#define BC_V_SIZE 0 675#define BC_M_SIZE (0x7<<BC_V_SIZE) 676 677#define BC_K_CONFIG \ 678 ((0x1<<BC_V_WE_OFF) | \ 679 (0x7<<BC_V_RD_WR_SPC) | \ 680 (0x4<<BC_V_WR_SPD) | \ 681 (0x4<<BC_V_RD_SPD) | \ 682 (0x1<<BC_V_SIZE)) 683 684/* 685** 686** DECchip 21164 Privileged Architecture Library Entry Offsets: 687** 688** Entry Name Offset (Hex) 689** 690** RESET 0000 691** IACCVIO 0080 692** INTERRUPT 0100 693** ITB_MISS 0180 694** DTB_MISS (Single) 0200 695** DTB_MISS (Double) 0280 696** UNALIGN 0300 697** D_FAULT 0380 698** MCHK 0400 699** OPCDEC 0480 700** ARITH 0500 701** FEN 0580 702** CALL_PAL (Privileged) 2000 703** CALL_PAL (Unprivileged) 3000 704** 705*/ 706 707#define PAL_RESET_ENTRY 0x0000 708#define PAL_IACCVIO_ENTRY 0x0080 709#define PAL_INTERRUPT_ENTRY 0x0100 710#define PAL_ITB_MISS_ENTRY 0x0180 711#define PAL_DTB_MISS_ENTRY 0x0200 712#define PAL_DOUBLE_MISS_ENTRY 0x0280 713#define PAL_UNALIGN_ENTRY 0x0300 714#define PAL_D_FAULT_ENTRY 0x0380 715#define PAL_MCHK_ENTRY 0x0400 716#define PAL_OPCDEC_ENTRY 0x0480 717#define PAL_ARITH_ENTRY 0x0500 718#define PAL_FEN_ENTRY 0x0580 719#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 720#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 721 722/* 723** 724** Architecturally Reserved Opcode (PALRES) Definitions: 725** 726*/ 727 728#define mtpr hw_mtpr 729#define mfpr hw_mfpr 730 731#define ldl_a hw_ldl/a 732#define ldq_a hw_ldq/a 733#define stq_a hw_stq/a 734#define stl_a hw_stl/a 735 736#define ldl_p hw_ldl/p 737#define ldq_p hw_ldq/p 738#define stl_p hw_stl/p 739#define stq_p hw_stq/p 740 741/* 742** Virtual PTE fetch variants of HW_LD. 743*/ 744#define ld_vpte hw_ldq/v 745 746/* 747** Physical mode load-lock and store-conditional variants of 748** HW_LD and HW_ST. 749*/ 750 751#define ldq_lp hw_ldq/pl 752#define stq_cp hw_stq/pc 753 754/* 755** 756** General Purpose Register Definitions: 757** 758*/ 759 760#define r0 $0 761#define r1 $1 762#define r2 $2 763#define r3 $3 764#define r4 $4 765#define r5 $5 766#define r6 $6 767#define r7 $7 768#define r8 $8 769#define r9 $9 770#define r10 $10 771#define r11 $11 772#define r12 $12 773#define r13 $13 774#define r14 $14 775#define r15 $15 776#define r16 $16 777#define r17 $17 778#define r18 $18 779#define r19 $19 780#define r20 $20 781#define r21 $21 782#define r22 $22 783#define r23 $23 784#define r24 $24 785#define r25 $25 786#define r26 $26 787#define r27 $27 788#define r28 $28 789#define r29 $29 790#define r30 $30 791#define r31 $31 792 793/* 794** 795** Floating Point Register Definitions: 796** 797*/ 798 799#define f0 $f0 800#define f1 $f1 801#define f2 $f2 802#define f3 $f3 803#define f4 $f4 804#define f5 $f5 805#define f6 $f6 806#define f7 $f7 807#define f8 $f8 808#define f9 $f9 809#define f10 $f10 810#define f11 $f11 811#define f12 $f12 812#define f13 $f13 813#define f14 $f14 814#define f15 $f15 815#define f16 $f16 816#define f17 $f17 817#define f18 $f18 818#define f19 $f19 819#define f20 $f20 820#define f21 $f21 821#define f22 $f22 822#define f23 $f23 823#define f24 $f24 824#define f25 $f25 825#define f26 $f26 826#define f27 $f27 827#define f28 $f28 828#define f29 $f29 829#define f30 $f30 830#define f31 $f31 831 832/* 833** 834** PAL Temporary Register Definitions: 835** 836*/ 837 838// covered by fetch distribution..pb Nov/95 839 840// #define pt0 0x140 841// #define pt1 0x141 842// #define pt2 0x142 843// #define pt3 0x143 844// #define pt4 0x144 845// #define pt5 0x145 846// #define pt6 0x146 847// #define pt7 0x147 848// #define pt8 0x148 849// #define pt9 0x149 850// #define pt10 0x14A 851// #define pt11 0x14B 852// #define pt12 0x14C 853// #define pt13 0x14D 854// #define pt14 0x14E 855// #define pt15 0x14F 856// #define pt16 0x150 857// #define pt17 0x151 858// #define pt18 0x152 859// #define pt19 0x153 860// #define pt20 0x154 861// #define pt21 0x155 862// #define pt22 0x156 863// #define pt23 0x157 864 865/* 866** PAL Shadow Registers: 867** 868** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 869** ICSR<SDE> = 1. 870*/ 871 872#define p0 r8 /* ITB/DTB Miss Scratch */ 873#define p1 r9 /* ITB/DTB Miss Scratch */ 874#define p2 r10 /* ITB/DTB Miss Scratch */ 875#define p3 r11 876// #define ps r11 /* Processor Status */ 877#define p4 r12 /* Local Scratch */ 878#define p5 r13 /* Local Scratch */ 879#define p6 r14 /* Local Scratch */ 880#define p7 r25 /* Local Scratch */ 881 882/* 883** SRM Defined State Definitions: 884*/ 885 886/* 887** This table is an accounting of the DECchip 21164 storage used to 888** implement the SRM defined state for OSF/1. 889** 890** IPR Name Internal Storage 891** -------- ---------------- 892** Processor Status ps, dtbCm, ipl, r11 893** Program Counter Ibox 894** Interrupt Entry ptEntInt 895** Arith Trap Entry ptEntArith 896** MM Fault Entry ptEntMM 897** Unaligned Access Entry ptEntUna 898** Instruction Fault Entry ptEntIF 899** Call System Entry ptEntSys 900** User Stack Pointer ptUsp 901** Kernel Stack Pointer ptKsp 902** Kernel Global Pointer ptKgp 903** System Value ptSysVal 904** Page Table Base Register ptPtbr 905** Virtual Page Table Base iVptBr, mVptBr 906** Process Control Block Base ptPcbb 907** Address Space Number itbAsn, dtbAsn 908** Cycle Counter cc, ccCtl 909** Float Point Enable icsr 910** Lock Flag Cbox/System 911** Unique PCB 912** Who-Am-I ptWhami 913*/ 914 915#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 916#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 917#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 918#define ptIntMask pt8 /* Interrupt Enable Mask */ 919#define ptEntSys pt9 /* Call System Dispatch Entry */ 920#define ptTrap pt11 921#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 922#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 923#if defined(KDEBUG) 924#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 925#endif /* KDEBUG */ 926#define ptMisc pt16 /* Miscellaneous Flags */ 927#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 928#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 929#define ptSysVal pt17 /* Per-Processor System Value */ 930#define ptUsp pt18 /* User Stack Pointer */ 931#define ptKsp pt19 /* Kernel Stack Pointer */ 932#define ptPtbr pt20 /* Page Table Base Register */ 933#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 934#define ptKgp pt22 /* Kernel Global Pointer */ 935#define ptPcbb pt23 /* Process Control Block Base */ 936 937/* 938** 939** Miscellaneous PAL State Flags (ptMisc) Bit Summary 940** 941** Extent Size Name Function 942** ------ ---- ---- --------------------------------- 943** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 944** <47:32> 16 MCHK Machine Check Error code 945** <31:16> 16 SCB System Control Block vector 946** <15:08> 8 WHAMI Who-Am-I identifier 947** <04:00> 5 MCES Machine Check Error Summary bits 948** 949*/ 950 951#define PT16_V_MCES 0 952#define PT16_V_WHAMI 8 953#define PT16_V_SCB 16 954#define PT16_V_MCHK 32 955#define PT16_V_SWAP 48 956 957#endif /* DC21164FROMGASSOURCES_INCLUDED */ 958