paljtoslave.S revision 8012
18012Ssaidi@eecs.umich.edu/* 28012Ssaidi@eecs.umich.eduCopyright (c) 2003, 2004 38012Ssaidi@eecs.umich.eduThe Regents of The University of Michigan 48012Ssaidi@eecs.umich.eduAll Rights Reserved 58012Ssaidi@eecs.umich.edu 68012Ssaidi@eecs.umich.eduThis code is part of the M5 simulator, developed by Nathan Binkert, 78012Ssaidi@eecs.umich.eduErik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 88012Ssaidi@eecs.umich.edufrom Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew 98012Ssaidi@eecs.umich.eduSchultz. 108012Ssaidi@eecs.umich.edu 118012Ssaidi@eecs.umich.eduPermission is granted to use, copy, create derivative works and 128012Ssaidi@eecs.umich.eduredistribute this software and such derivative works for any purpose, 138012Ssaidi@eecs.umich.eduso long as the copyright notice above, this grant of permission, and 148012Ssaidi@eecs.umich.eduthe disclaimer below appear in all copies made; and so long as the 158012Ssaidi@eecs.umich.eduname of The University of Michigan is not used in any advertising or 168012Ssaidi@eecs.umich.edupublicity pertaining to the use or distribution of this software 178012Ssaidi@eecs.umich.eduwithout specific, written prior authorization. 188012Ssaidi@eecs.umich.edu 198012Ssaidi@eecs.umich.eduTHIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 208012Ssaidi@eecs.umich.eduUNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT 218012Ssaidi@eecs.umich.eduWARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR 228012Ssaidi@eecs.umich.eduIMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF 238012Ssaidi@eecs.umich.eduMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF 248012Ssaidi@eecs.umich.eduTHE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, 258012Ssaidi@eecs.umich.eduINCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL 268012Ssaidi@eecs.umich.eduDAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION 278012Ssaidi@eecs.umich.eduWITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER 288012Ssaidi@eecs.umich.eduADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 298012Ssaidi@eecs.umich.edu*/ 308012Ssaidi@eecs.umich.edu/* 318012Ssaidi@eecs.umich.eduCopyright 1993 Hewlett-Packard Development Company, L.P. 328012Ssaidi@eecs.umich.edu 338012Ssaidi@eecs.umich.eduPermission is hereby granted, free of charge, to any person obtaining a copy of 348012Ssaidi@eecs.umich.eduthis software and associated documentation files (the "Software"), to deal in 358012Ssaidi@eecs.umich.eduthe Software without restriction, including without limitation the rights to 368012Ssaidi@eecs.umich.eduuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 378012Ssaidi@eecs.umich.eduof the Software, and to permit persons to whom the Software is furnished to do 388012Ssaidi@eecs.umich.eduso, subject to the following conditions: 398012Ssaidi@eecs.umich.edu 408012Ssaidi@eecs.umich.eduThe above copyright notice and this permission notice shall be included in all 418012Ssaidi@eecs.umich.educopies or substantial portions of the Software. 428012Ssaidi@eecs.umich.edu 438012Ssaidi@eecs.umich.eduTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 448012Ssaidi@eecs.umich.eduIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 458012Ssaidi@eecs.umich.eduFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 468012Ssaidi@eecs.umich.eduAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 478012Ssaidi@eecs.umich.eduLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 488012Ssaidi@eecs.umich.eduOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 498012Ssaidi@eecs.umich.eduSOFTWARE. 508012Ssaidi@eecs.umich.edu*/ 518008Ssaidi@eecs.umich.edu#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 528008Ssaidi@eecs.umich.edu#include "ev5_defs.h" 538008Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" // OSF/1 specific definitions 548008Ssaidi@eecs.umich.edu#include "fromHudsonMacros.h" // Global macro definitions 558008Ssaidi@eecs.umich.edu#include "ev5_impure.h" // Scratch & logout area data structures 568008Ssaidi@eecs.umich.edu#include "platform.h" // Platform specific definitions 578008Ssaidi@eecs.umich.edu 588008Ssaidi@eecs.umich.edu 598008Ssaidi@eecs.umich.edu .global palJToSlave 608008Ssaidi@eecs.umich.edu .text 3 618008Ssaidi@eecs.umich.edu 628008Ssaidi@eecs.umich.edu /* 638008Ssaidi@eecs.umich.edu * args: 648008Ssaidi@eecs.umich.edu a0: here 658008Ssaidi@eecs.umich.edu a1: boot location 668008Ssaidi@eecs.umich.edu a2: CSERVE_J_KTOPAL 678008Ssaidi@eecs.umich.edu a3: restrart_pv 688008Ssaidi@eecs.umich.edu a4: vptb 698008Ssaidi@eecs.umich.edu a5: my_rpb 708008Ssaidi@eecs.umich.edu 718008Ssaidi@eecs.umich.edu */ 728008Ssaidi@eecs.umich.edupalJToSlave: 738008Ssaidi@eecs.umich.edu 748008Ssaidi@eecs.umich.edu /* 758008Ssaidi@eecs.umich.edu * SRM Console Architecture III 3-26 768008Ssaidi@eecs.umich.edu */ 778008Ssaidi@eecs.umich.edu 788008Ssaidi@eecs.umich.edu ALIGN_BRANCH 798008Ssaidi@eecs.umich.edu 808008Ssaidi@eecs.umich.edu bis a3, zero, pv 818008Ssaidi@eecs.umich.edu bis zero, zero, t11 828008Ssaidi@eecs.umich.edu bis zero, zero, ra 838008Ssaidi@eecs.umich.edu 848008Ssaidi@eecs.umich.edu /* Point the Vptbr to a2 */ 858008Ssaidi@eecs.umich.edu 868008Ssaidi@eecs.umich.edu mtpr a4, mVptBr // Load Mbox copy 878008Ssaidi@eecs.umich.edu mtpr a4, iVptBr // Load Ibox copy 888008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 898008Ssaidi@eecs.umich.edu 908008Ssaidi@eecs.umich.edu /* Turn on superpage mapping in the mbox and icsr */ 918008Ssaidi@eecs.umich.edu lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 928008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 938008Ssaidi@eecs.umich.edu mtpr t0, mcsr // Set the super page mode enable bit 948008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 958008Ssaidi@eecs.umich.edu 968008Ssaidi@eecs.umich.edu lda t0, 0(zero) 978008Ssaidi@eecs.umich.edu mtpr t0, dtbAsn 988008Ssaidi@eecs.umich.edu mtpr t0, itbAsn 998008Ssaidi@eecs.umich.edu 1008008Ssaidi@eecs.umich.edu LDLI (t1,0x20000000) 1018008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1028008Ssaidi@eecs.umich.edu mfpr t0, icsr // Enable superpage mapping 1038008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1048008Ssaidi@eecs.umich.edu bis t0, t1, t0 1058008Ssaidi@eecs.umich.edu mtpr t0, icsr 1068008Ssaidi@eecs.umich.edu 1078008Ssaidi@eecs.umich.edu STALL // Required stall to update chip ... 1088008Ssaidi@eecs.umich.edu STALL 1098008Ssaidi@eecs.umich.edu STALL 1108008Ssaidi@eecs.umich.edu STALL 1118008Ssaidi@eecs.umich.edu STALL 1128008Ssaidi@eecs.umich.edu 1138008Ssaidi@eecs.umich.edu ldq_p s0, PCB_Q_PTBR(a5) 1148008Ssaidi@eecs.umich.edu sll s0, VA_S_OFF, s0 // Shift PTBR into position 1158008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1168008Ssaidi@eecs.umich.edu mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 1178008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1188008Ssaidi@eecs.umich.edu ldq_p sp, PCB_Q_KSP(a5) 1198008Ssaidi@eecs.umich.edu 1208008Ssaidi@eecs.umich.edu //mtpr a0, excAddr // Load the dispatch address. 1218008Ssaidi@eecs.umich.edu //STALL // don't dual issue the load with mtpr -pb 1228008Ssaidi@eecs.umich.edu //bis a3, zero, a0 // first free PFN 1238008Ssaidi@eecs.umich.edu // ldq_p a1, PCB_Q_PTBR(a5) // ptbr 1248008Ssaidi@eecs.umich.edu 1258008Ssaidi@eecs.umich.edu //ldq_p a2, 24(zero) // argc 1268008Ssaidi@eecs.umich.edu //ldq_p a3, 32(zero) // argv 1278008Ssaidi@eecs.umich.edu //ldq_p a4, 40(zero) // environ 1288008Ssaidi@eecs.umich.edu //lda a5, 0(zero) // osf_param 1298008Ssaidi@eecs.umich.edu //STALL // don't dual issue the load with mtpr -pb 1308008Ssaidi@eecs.umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1318008Ssaidi@eecs.umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1328008Ssaidi@eecs.umich.edu 1338008Ssaidi@eecs.umich.edu 1348008Ssaidi@eecs.umich.edu mtpr a1, excAddr // Load the dispatch address. 1358008Ssaidi@eecs.umich.edu 1368008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1378008Ssaidi@eecs.umich.edu STALL // don't dual issue the load with mtpr -pb 1388008Ssaidi@eecs.umich.edu mtpr zero, dtbIa // Flush all D-stream TB entries 1398008Ssaidi@eecs.umich.edu mtpr zero, itbIa // Flush all I-stream TB entries 1408008Ssaidi@eecs.umich.edu br zero, 2f 1418008Ssaidi@eecs.umich.edu 1428008Ssaidi@eecs.umich.edu ALIGN_BLOCK 1438008Ssaidi@eecs.umich.edu 1448008Ssaidi@eecs.umich.edu2: NOP 1458008Ssaidi@eecs.umich.edu mtpr zero, icFlush // Flush the icache. 1468008Ssaidi@eecs.umich.edu NOP 1478008Ssaidi@eecs.umich.edu NOP 1488008Ssaidi@eecs.umich.edu 1498008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 1-10 1508008Ssaidi@eecs.umich.edu NOP 1518008Ssaidi@eecs.umich.edu NOP 1528008Ssaidi@eecs.umich.edu NOP 1538008Ssaidi@eecs.umich.edu NOP 1548008Ssaidi@eecs.umich.edu NOP 1558008Ssaidi@eecs.umich.edu NOP 1568008Ssaidi@eecs.umich.edu NOP 1578008Ssaidi@eecs.umich.edu NOP 1588008Ssaidi@eecs.umich.edu NOP 1598008Ssaidi@eecs.umich.edu 1608008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 11-20 1618008Ssaidi@eecs.umich.edu NOP 1628008Ssaidi@eecs.umich.edu NOP 1638008Ssaidi@eecs.umich.edu NOP 1648008Ssaidi@eecs.umich.edu NOP 1658008Ssaidi@eecs.umich.edu NOP 1668008Ssaidi@eecs.umich.edu NOP 1678008Ssaidi@eecs.umich.edu NOP 1688008Ssaidi@eecs.umich.edu NOP 1698008Ssaidi@eecs.umich.edu NOP 1708008Ssaidi@eecs.umich.edu 1718008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 21-30 1728008Ssaidi@eecs.umich.edu NOP 1738008Ssaidi@eecs.umich.edu NOP 1748008Ssaidi@eecs.umich.edu NOP 1758008Ssaidi@eecs.umich.edu NOP 1768008Ssaidi@eecs.umich.edu NOP 1778008Ssaidi@eecs.umich.edu NOP 1788008Ssaidi@eecs.umich.edu NOP 1798008Ssaidi@eecs.umich.edu NOP 1808008Ssaidi@eecs.umich.edu NOP 1818008Ssaidi@eecs.umich.edu 1828008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 31-40 1838008Ssaidi@eecs.umich.edu NOP 1848008Ssaidi@eecs.umich.edu NOP 1858008Ssaidi@eecs.umich.edu NOP 1868008Ssaidi@eecs.umich.edu NOP 1878008Ssaidi@eecs.umich.edu NOP 1888008Ssaidi@eecs.umich.edu NOP 1898008Ssaidi@eecs.umich.edu NOP 1908008Ssaidi@eecs.umich.edu NOP 1918008Ssaidi@eecs.umich.edu NOP 1928008Ssaidi@eecs.umich.edu 1938008Ssaidi@eecs.umich.edu 1948008Ssaidi@eecs.umich.edu 1958008Ssaidi@eecs.umich.edu NOP // Required NOPs ... 41-44 1968008Ssaidi@eecs.umich.edu NOP 1978008Ssaidi@eecs.umich.edu NOP 1988008Ssaidi@eecs.umich.edu NOP 1998008Ssaidi@eecs.umich.edu 2008008Ssaidi@eecs.umich.edu hw_rei_stall // Dispatch to kernel 2018008Ssaidi@eecs.umich.edu 202