paljtoslave.S revision 8012
1/* 2Copyright (c) 2003, 2004 3The Regents of The University of Michigan 4All Rights Reserved 5 6This code is part of the M5 simulator, developed by Nathan Binkert, 7Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions 8from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew 9Schultz. 10 11Permission is granted to use, copy, create derivative works and 12redistribute this software and such derivative works for any purpose, 13so long as the copyright notice above, this grant of permission, and 14the disclaimer below appear in all copies made; and so long as the 15name of The University of Michigan is not used in any advertising or 16publicity pertaining to the use or distribution of this software 17without specific, written prior authorization. 18 19THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 20UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT 21WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR 22IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF 23MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF 24THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, 25INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL 26DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION 27WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER 28ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 29*/ 30/* 31Copyright 1993 Hewlett-Packard Development Company, L.P. 32 33Permission is hereby granted, free of charge, to any person obtaining a copy of 34this software and associated documentation files (the "Software"), to deal in 35the Software without restriction, including without limitation the rights to 36use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 37of the Software, and to permit persons to whom the Software is furnished to do 38so, subject to the following conditions: 39 40The above copyright notice and this permission notice shall be included in all 41copies or substantial portions of the Software. 42 43THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 44IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 45FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 46AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 47LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 48OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 49SOFTWARE. 50*/ 51#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions 52#include "ev5_defs.h" 53#include "fromHudsonOsf.h" // OSF/1 specific definitions 54#include "fromHudsonMacros.h" // Global macro definitions 55#include "ev5_impure.h" // Scratch & logout area data structures 56#include "platform.h" // Platform specific definitions 57 58 59 .global palJToSlave 60 .text 3 61 62 /* 63 * args: 64 a0: here 65 a1: boot location 66 a2: CSERVE_J_KTOPAL 67 a3: restrart_pv 68 a4: vptb 69 a5: my_rpb 70 71 */ 72palJToSlave: 73 74 /* 75 * SRM Console Architecture III 3-26 76 */ 77 78 ALIGN_BRANCH 79 80 bis a3, zero, pv 81 bis zero, zero, t11 82 bis zero, zero, ra 83 84 /* Point the Vptbr to a2 */ 85 86 mtpr a4, mVptBr // Load Mbox copy 87 mtpr a4, iVptBr // Load Ibox copy 88 STALL // don't dual issue the load with mtpr -pb 89 90 /* Turn on superpage mapping in the mbox and icsr */ 91 lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP> 92 STALL // don't dual issue the load with mtpr -pb 93 mtpr t0, mcsr // Set the super page mode enable bit 94 STALL // don't dual issue the load with mtpr -pb 95 96 lda t0, 0(zero) 97 mtpr t0, dtbAsn 98 mtpr t0, itbAsn 99 100 LDLI (t1,0x20000000) 101 STALL // don't dual issue the load with mtpr -pb 102 mfpr t0, icsr // Enable superpage mapping 103 STALL // don't dual issue the load with mtpr -pb 104 bis t0, t1, t0 105 mtpr t0, icsr 106 107 STALL // Required stall to update chip ... 108 STALL 109 STALL 110 STALL 111 STALL 112 113 ldq_p s0, PCB_Q_PTBR(a5) 114 sll s0, VA_S_OFF, s0 // Shift PTBR into position 115 STALL // don't dual issue the load with mtpr -pb 116 mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1 117 STALL // don't dual issue the load with mtpr -pb 118 ldq_p sp, PCB_Q_KSP(a5) 119 120 //mtpr a0, excAddr // Load the dispatch address. 121 //STALL // don't dual issue the load with mtpr -pb 122 //bis a3, zero, a0 // first free PFN 123 // ldq_p a1, PCB_Q_PTBR(a5) // ptbr 124 125 //ldq_p a2, 24(zero) // argc 126 //ldq_p a3, 32(zero) // argv 127 //ldq_p a4, 40(zero) // environ 128 //lda a5, 0(zero) // osf_param 129 //STALL // don't dual issue the load with mtpr -pb 130 mtpr zero, dtbIa // Flush all D-stream TB entries 131 mtpr zero, itbIa // Flush all I-stream TB entries 132 133 134 mtpr a1, excAddr // Load the dispatch address. 135 136 STALL // don't dual issue the load with mtpr -pb 137 STALL // don't dual issue the load with mtpr -pb 138 mtpr zero, dtbIa // Flush all D-stream TB entries 139 mtpr zero, itbIa // Flush all I-stream TB entries 140 br zero, 2f 141 142 ALIGN_BLOCK 143 1442: NOP 145 mtpr zero, icFlush // Flush the icache. 146 NOP 147 NOP 148 149 NOP // Required NOPs ... 1-10 150 NOP 151 NOP 152 NOP 153 NOP 154 NOP 155 NOP 156 NOP 157 NOP 158 NOP 159 160 NOP // Required NOPs ... 11-20 161 NOP 162 NOP 163 NOP 164 NOP 165 NOP 166 NOP 167 NOP 168 NOP 169 NOP 170 171 NOP // Required NOPs ... 21-30 172 NOP 173 NOP 174 NOP 175 NOP 176 NOP 177 NOP 178 NOP 179 NOP 180 NOP 181 182 NOP // Required NOPs ... 31-40 183 NOP 184 NOP 185 NOP 186 NOP 187 NOP 188 NOP 189 NOP 190 NOP 191 NOP 192 193 194 195 NOP // Required NOPs ... 41-44 196 NOP 197 NOP 198 NOP 199 200 hw_rei_stall // Dispatch to kernel 201 202