1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test01.cpp -- Test sc_vector 23 24 Original Author: Philipp A. Hartmann, OFFIS, 2010-01-10 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40using sc_core::sc_vector; 41 42SC_MODULE( sub_module ) 43{ 44 sc_in<bool> in; 45 SC_CTOR(sub_module) {} 46}; 47 48SC_MODULE( module ) 49{ 50 // vector of sub-modules 51 sc_vector< sub_module > m_sub_vec; 52 53 // vector of ports 54 sc_vector< sc_in<bool> > in_vec; 55 56 module( sc_core::sc_module_name, unsigned n_sub ) 57 : m_sub_vec( "sub_modules", n_sub ) // set name prefix, and create sub-modules 58 // , in_vec() // use default constructor 59 // , in_vec( "in_vec" ) // set name prefix 60 { 61 // delayed initialisation of port vector 62 // here with default prefix sc_core::sc_gen_unique_name("vector") 63 in_vec.init( n_sub ); 64 65 // bind ports of sub-modules -- sc_assemble_vector 66 sc_assemble_vector( m_sub_vec, &sub_module::in ).bind( in_vec ); 67 } 68}; 69 70int sc_main(int , char* []) 71{ 72 module m("dut", 4); 73 74 std::vector<sc_object*> children = m.get_child_objects(); 75 76 for (size_t i=0; i<children.size(); ++i ) 77 cout << children[i]->name() << " - " 78 << children[i]->kind() 79 << endl; 80 81 cout << "Program completed" << endl; 82 return 0; 83} 84