1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38// test of signal port tracing. 39 40#include "systemc.h" 41 42SC_MODULE( mod_a ) 43{ 44 sc_in_clk clk; 45 46 sc_in<int> in_int; 47 sc_in<bool> in_bool; 48 sc_in<sc_logic> in_logic; 49 sc_in_resolved in_resolved; 50 sc_in_rv<1> in_rv1; 51 52 sc_out<int> out_int; 53 sc_out<bool> out_bool; 54 sc_out<sc_logic> out_logic; 55 sc_out_resolved out_resolved; 56 sc_out_rv<1> out_rv1; 57 58 void main_action() 59 { 60 int a_int = 0; 61 bool a_bool = false; 62 sc_logic a_logic = SC_LOGIC_X; 63 sc_logic a_resolved = SC_LOGIC_X; 64 sc_lv<1> a_rv1 = sc_lv<1>( SC_LOGIC_X ); 65 66 wait(); 67 68 while( true ) { 69 out_int = a_int; 70 out_bool = a_bool; 71 out_logic = a_logic; 72 out_resolved = a_resolved; 73 out_rv1 = a_rv1; 74 75 a_int ++; 76 a_bool = ! a_bool; 77 a_logic = sc_dt::sc_logic_value_t( a_int % 4 ); 78 a_resolved = a_logic; 79 a_rv1 = sc_lv<1>( a_logic ); 80 81 wait(); 82 } 83 } 84 85 SC_CTOR( mod_a ) 86 { 87 SC_THREAD( main_action ); 88 sensitive << clk.pos(); 89 } 90}; 91 92int 93sc_main( int, char*[] ) 94{ 95 sc_clock clk; 96 97 sc_signal<int> sig_int; 98 sc_signal<bool> sig_bool; 99 sc_signal<sc_logic> sig_logic; 100 sc_signal_resolved sig_resolved; 101 sc_signal_rv<1> sig_rv1; 102 103 mod_a a( "a" ); 104 105 a.clk( clk ); 106 107 a.in_int( sig_int ); 108 a.in_bool( sig_bool ); 109 a.in_logic( sig_logic ); 110 a.in_resolved( sig_resolved ); 111 a.in_rv1( sig_rv1 ); 112 113 a.out_int( sig_int ); 114 a.out_bool( sig_bool ); 115 a.out_logic( sig_logic ); 116 a.out_resolved( sig_resolved ); 117 a.out_rv1( sig_rv1 ); 118 119 sc_trace_file* tf = sc_create_vcd_trace_file( "test" ); 120 121 sc_trace( tf, sig_int, "sig_int" ); 122 sc_trace( tf, sig_bool, "sig_bool" ); 123 sc_trace( tf, sig_logic, "sig_logic" ); 124 sc_trace( tf, sig_resolved, "sig_resolved" ); 125 sc_trace( tf, sig_rv1, "sig_rv1" ); 126 127 sc_trace( tf, a.in_int, "a.in_int" ); 128 sc_trace( tf, a.in_bool, "a.in_bool" ); 129 sc_trace( tf, a.in_logic, "a.in_logic" ); 130 sc_trace( tf, a.in_resolved, "a.in_resolved" ); 131 sc_trace( tf, a.in_rv1, "a.in_rv1" ); 132 133 sc_trace( tf, a.out_int, "a.out_int" ); 134 sc_trace( tf, a.out_bool, "a.out_bool" ); 135 sc_trace( tf, a.out_logic, "a.out_logic" ); 136 sc_trace( tf, a.out_resolved, "a.out_resolved" ); 137 sc_trace( tf, a.out_rv1, "a.out_rv1" ); 138 139 sc_start( 10, SC_NS ); 140 141 sc_close_vcd_trace_file( tf ); 142 143 return 0; 144} 145