1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  main.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38                /***************************************/
39                /* Main Filename: 	main.cc        */
40                /***************************************/
41
42#include "reset.h"
43#include "display.h"
44#include "prime_numgen.h"
45
46int sc_main(int ac, char *av[])
47{
48
49// Signal Instantiation
50  sc_signal<bool>         reset		("reset");
51  sc_signal<bool>         prime_ready	("prime_ready");
52  signal_bool_vector      prime		("prime");
53
54// Clock Instantiation
55  sc_clock 	clk ("CLK", 6, SC_NS, 0.5, 10, SC_NS, false);	// 167 Mhz
56
57// Process Instantiation
58  prime_numgen	D1 ("D1", clk, reset, prime_ready, prime);
59
60  resetp	T1 ("T1", clk, reset);
61
62  displayp	T2 ("T2", clk, prime_ready, prime);
63
64// Simulation Run Control
65  sc_start();
66  return 0;
67}
68