1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  reset_stim.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include "define.h"
39
40/******************************************************************************/
41/***************************   reset_stim Function       **********************/
42/******************************************************************************/
43bool_vector8 mem [LIMIT + 1]; // Stimulus input memory
44
45SC_MODULE( RESET_STIM )
46{
47    SC_HAS_PROCESS( RESET_STIM );
48
49    sc_in_clk clk;
50
51  /*** Input and Output Ports ***/
52  sc_signal<bool>& 	ready;
53  sc_signal<bool>& 	reset;
54  sc_signal<int>&	addr;
55
56  /*** Constructor ***/
57  RESET_STIM (   sc_module_name    	NAME,
58                      sc_clock&    TICK_N,
59                      sc_signal<bool>&  READY,
60                      sc_signal<bool>&  RESET,
61  		      sc_signal<int>&	ADDR   )
62
63    :
64		ready (READY),
65		reset (RESET),
66		addr  (ADDR)
67
68    {
69		clk (TICK_N);
70        SC_CTHREAD( entry, clk.neg() );
71    }
72
73  /*** Call to Process Functionality ***/
74  void entry();
75
76};
77
78void
79RESET_STIM::entry()
80{
81
82//  LOAD MEMORY WITH DATA AT TIME ZERO
83
84  ifstream 		stimulus ("add_chain/add_chain.dat");
85  char			buffer[WIDTH+1];
86
87  for(int i=1; i < LIMIT+1; i++) {
88      stimulus >> buffer;
89      mem[i] = buffer;
90  }
91
92  stimulus.close();
93
94//  INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES
95
96  reset.write(0);	// reset = 0
97  addr.write(1);	// addr = 1
98  wait(2);
99
100  reset.write(1);	// reset = 1
101  wait();
102
103// WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION
104
105  // do { wait(); } while (addr == LIMIT);
106  do { wait(); } while (!(addr == LIMIT));
107  wait(LATENCY);
108  do { wait(); } while (ready != 1);
109  sc_stop();
110  halt();
111}
112