1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 display.h -- 23 24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 39#include "common.h" 40 41SC_MODULE( display ) 42{ 43 SC_HAS_PROCESS( display ); 44 45 sc_in_clk clk; 46 47 const sc_signal_bool_vector4& in_data1; // Input port 48 const sc_signal_bool_vector4& in_data2; // Input port 49 const sc_signal_bool_vector6& in_data3; // Input port 50 const sc_signal_bool_vector6& in_data4; // Input port 51 const sc_signal_bool_vector8& in_data5; // Input port 52 const sc_signal_bool_vector8& in_data6; // Input port 53 const sc_signal<bool>& in_valid; 54 55 display( sc_module_name NAME, 56 sc_clock& CLK, 57 const sc_signal_bool_vector4& IN_DATA1, 58 const sc_signal_bool_vector4& IN_DATA2, 59 const sc_signal_bool_vector6& IN_DATA3, 60 const sc_signal_bool_vector6& IN_DATA4, 61 const sc_signal_bool_vector8& IN_DATA5, 62 const sc_signal_bool_vector8& IN_DATA6, 63 const sc_signal<bool>& IN_VALID 64 ) 65 : 66 in_data1(IN_DATA1), 67 in_data2(IN_DATA2), 68 in_data3(IN_DATA3), 69 in_data4(IN_DATA4), 70 in_data5(IN_DATA5), 71 in_data6(IN_DATA6), 72 in_valid(IN_VALID) 73 { 74 clk(CLK); 75 SC_CTHREAD( entry, clk.pos() ); 76 } 77 78 void entry(); 79}; 80 81// EOF 82