vptr.hh revision 5191
1712SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3712SN/A * All rights reserved.
4712SN/A *
5712SN/A * Redistribution and use in source and binary forms, with or without
6712SN/A * modification, are permitted provided that the following conditions are
7712SN/A * met: redistributions of source code must retain the above copyright
8712SN/A * notice, this list of conditions and the following disclaimer;
9712SN/A * redistributions in binary form must reproduce the above copyright
10712SN/A * notice, this list of conditions and the following disclaimer in the
11712SN/A * documentation and/or other materials provided with the distribution;
12712SN/A * neither the name of the copyright holders nor the names of its
13712SN/A * contributors may be used to endorse or promote products derived from
14712SN/A * this software without specific prior written permission.
15712SN/A *
16712SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18712SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19712SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20712SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21712SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22712SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23712SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24712SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25712SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26712SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
29712SN/A */
30712SN/A
311354SN/A#ifndef __ARCH_ALPHA_VPTR_HH__
321354SN/A#define __ARCH_ALPHA_VPTR_HH__
33712SN/A
342170SN/A#include "arch/vtophys.hh"
352080SN/A#include "arch/isa_traits.hh"
365191Ssaidi@eecs.umich.edu#include "mem/vport.hh"
37712SN/A
382680Sktlim@umich.educlass ThreadContext;
39712SN/A
40712SN/Atemplate <class T>
41712SN/Aclass VPtr
42712SN/A{
43712SN/A  public:
44712SN/A    typedef T Type;
45712SN/A
465191Ssaidi@eecs.umich.edu  protected:
472680Sktlim@umich.edu    ThreadContext *tc;
48712SN/A    Addr ptr;
495191Ssaidi@eecs.umich.edu    Addr buffer[(sizeof(T)-1)/sizeof(Addr) + 1];
50712SN/A
51712SN/A  public:
525191Ssaidi@eecs.umich.edu    explicit VPtr(ThreadContext *_tc, Addr p = 0)
535191Ssaidi@eecs.umich.edu        : tc(_tc), ptr(p)
545191Ssaidi@eecs.umich.edu    {
555191Ssaidi@eecs.umich.edu        refresh();
565191Ssaidi@eecs.umich.edu    }
57712SN/A
58712SN/A    template <class U>
595191Ssaidi@eecs.umich.edu    VPtr(const VPtr<U> &vp)
605191Ssaidi@eecs.umich.edu        : tc(vp.tc), ptr(vp.ptr)
615191Ssaidi@eecs.umich.edu    {
625191Ssaidi@eecs.umich.edu        refresh();
635191Ssaidi@eecs.umich.edu    }
64712SN/A
655191Ssaidi@eecs.umich.edu    ~VPtr()
665191Ssaidi@eecs.umich.edu    {}
675191Ssaidi@eecs.umich.edu
685191Ssaidi@eecs.umich.edu    void
695191Ssaidi@eecs.umich.edu    refresh()
705191Ssaidi@eecs.umich.edu    {
715191Ssaidi@eecs.umich.edu        if (!ptr)
725191Ssaidi@eecs.umich.edu            return;
735191Ssaidi@eecs.umich.edu
745191Ssaidi@eecs.umich.edu        VirtualPort *port = tc->getVirtPort(tc);
755191Ssaidi@eecs.umich.edu        port->readBlob(ptr, buffer, sizeof(T));
765191Ssaidi@eecs.umich.edu        tc->delVirtPort(port);
775191Ssaidi@eecs.umich.edu    }
785191Ssaidi@eecs.umich.edu
795191Ssaidi@eecs.umich.edu    bool
805191Ssaidi@eecs.umich.edu    operator!() const
81712SN/A    {
82712SN/A        return ptr == 0;
83712SN/A    }
84712SN/A
855191Ssaidi@eecs.umich.edu    VPtr<T>
865191Ssaidi@eecs.umich.edu    operator+(int offset)
87712SN/A    {
885191Ssaidi@eecs.umich.edu        return VPtr<T>(tc, ptr + offset);
89712SN/A    }
90712SN/A
915191Ssaidi@eecs.umich.edu    const VPtr<T> &
925191Ssaidi@eecs.umich.edu    operator+=(int offset)
93712SN/A    {
94712SN/A        ptr += offset;
955191Ssaidi@eecs.umich.edu        refresh();
96712SN/A
97712SN/A        return *this;
98712SN/A    }
99712SN/A
1005191Ssaidi@eecs.umich.edu    const VPtr<T> &
1015191Ssaidi@eecs.umich.edu    operator=(Addr p)
102712SN/A    {
103712SN/A        ptr = p;
1045191Ssaidi@eecs.umich.edu        refresh();
105712SN/A
106712SN/A        return *this;
107712SN/A    }
108712SN/A
109712SN/A    template <class U>
1105191Ssaidi@eecs.umich.edu    const VPtr<T> &
1115191Ssaidi@eecs.umich.edu    operator=(const VPtr<U> &vp)
112712SN/A    {
1135191Ssaidi@eecs.umich.edu        tc = vp.tc;
1145191Ssaidi@eecs.umich.edu        ptr = vp.ptr;
1155191Ssaidi@eecs.umich.edu        refresh();
116712SN/A
117712SN/A        return *this;
118712SN/A    }
119712SN/A
120712SN/A    operator T *()
121712SN/A    {
1225191Ssaidi@eecs.umich.edu        return (T *)buffer;
123712SN/A    }
124712SN/A
1255191Ssaidi@eecs.umich.edu    T *
1265191Ssaidi@eecs.umich.edu    operator->()
127712SN/A    {
1285191Ssaidi@eecs.umich.edu        return (T *)buffer;
129712SN/A    }
130712SN/A
1315191Ssaidi@eecs.umich.edu    T &
1325191Ssaidi@eecs.umich.edu    operator*()
133712SN/A    {
1345191Ssaidi@eecs.umich.edu        return *(T *)buffer;
135712SN/A    }
136712SN/A};
137712SN/A
1381354SN/A#endif // __ARCH_ALPHA_VPTR_HH__
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