system.hh revision 12680
12SN/A/* 212680Sgiacomo.travaglini@arm.com * Copyright (c) 2012, 2014, 2018 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5111911SBrandon.Potter@amd.com#include <unordered_map> 529645SAndreas.Sandberg@ARM.com#include <utility> 5375SN/A#include <vector> 542SN/A 5510466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 562439SN/A#include "base/loader/symtab.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 6012680Sgiacomo.travaglini@arm.com#include "mem/mem_master.hh" 618703Sandreas.hansson@arm.com#include "mem/mem_object.hh" 6211911SBrandon.Potter@amd.com#include "mem/physical.hh" 632520SN/A#include "mem/port.hh" 649847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 654762Snate@binkert.org#include "params/System.hh" 6611911SBrandon.Potter@amd.com#include "sim/futex_map.hh" 6711909SBrandon.Potter@amd.com#include "sim/se_signal.hh" 686658Snate@binkert.org 6910494Sandreas.hansson@arm.com/** 7010494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7110494Sandreas.hansson@arm.com * actually have the definition. 7210494Sandreas.hansson@arm.com */ 7310494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7410494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7511911SBrandon.Potter@amd.com 7610494Sandreas.hansson@arm.com#endif 7710494Sandreas.hansson@arm.com 788769Sgblack@eecs.umich.educlass BaseRemoteGDB; 7911839SCurtis.Dunham@arm.comclass KvmVM; 801634SN/Aclass ObjectFile; 818769Sgblack@eecs.umich.educlass ThreadContext; 822SN/A 838703Sandreas.hansson@arm.comclass System : public MemObject 842SN/A{ 858703Sandreas.hansson@arm.com private: 868703Sandreas.hansson@arm.com 878703Sandreas.hansson@arm.com /** 888703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 898703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 908703Sandreas.hansson@arm.com * not have a port of their own. 918703Sandreas.hansson@arm.com */ 928922Swilliam.wang@arm.com class SystemPort : public MasterPort 938703Sandreas.hansson@arm.com { 948703Sandreas.hansson@arm.com public: 958703Sandreas.hansson@arm.com 968703Sandreas.hansson@arm.com /** 978703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 988703Sandreas.hansson@arm.com */ 998703Sandreas.hansson@arm.com SystemPort(const std::string &_name, MemObject *_owner) 1008922Swilliam.wang@arm.com : MasterPort(_name, _owner) 1018703Sandreas.hansson@arm.com { } 10211169Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) override 1038703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10411169Sandreas.hansson@arm.com void recvReqRetry() override 1058922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1068703Sandreas.hansson@arm.com }; 1078703Sandreas.hansson@arm.com 1088703Sandreas.hansson@arm.com SystemPort _systemPort; 1098703Sandreas.hansson@arm.com 110603SN/A public: 1112901Ssaidi@eecs.umich.edu 1128703Sandreas.hansson@arm.com /** 1138706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1148706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1158706Sandreas.hansson@arm.com */ 11611169Sandreas.hansson@arm.com void init() override; 1178706Sandreas.hansson@arm.com 1188706Sandreas.hansson@arm.com /** 1198852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1208703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1218703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1228703Sandreas.hansson@arm.com * the memory system. 1238703Sandreas.hansson@arm.com * 1248852Sandreas.hansson@arm.com * @return a reference to the system port we own 1258703Sandreas.hansson@arm.com */ 1268922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1278703Sandreas.hansson@arm.com 1288703Sandreas.hansson@arm.com /** 1298703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1308703Sandreas.hansson@arm.com */ 1319294Sandreas.hansson@arm.com BaseMasterPort& getMasterPort(const std::string &if_name, 13211169Sandreas.hansson@arm.com PortID idx = InvalidPortID) override; 1338703Sandreas.hansson@arm.com 1349524SAndreas.Sandberg@ARM.com /** @{ */ 1359524SAndreas.Sandberg@ARM.com /** 1369524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1379524SAndreas.Sandberg@ARM.com * 1389524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1399524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1409524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1419524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1429524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1439524SAndreas.Sandberg@ARM.com */ 1449524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1459524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1469524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1474762Snate@binkert.org } 1482901Ssaidi@eecs.umich.edu 1499524SAndreas.Sandberg@ARM.com /** 1509524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1519524SAndreas.Sandberg@ARM.com * 1529524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1539524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1549524SAndreas.Sandberg@ARM.com */ 1559524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1569524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1579524SAndreas.Sandberg@ARM.com } 1589524SAndreas.Sandberg@ARM.com 1599524SAndreas.Sandberg@ARM.com /** 1609524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1619524SAndreas.Sandberg@ARM.com * 1629524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1639524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1649524SAndreas.Sandberg@ARM.com */ 1659524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1669524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1679524SAndreas.Sandberg@ARM.com } 1689524SAndreas.Sandberg@ARM.com /** @} */ 1699524SAndreas.Sandberg@ARM.com 1709524SAndreas.Sandberg@ARM.com /** @{ */ 1719524SAndreas.Sandberg@ARM.com /** 1729524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1739524SAndreas.Sandberg@ARM.com * 1749524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1759524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1769524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1779524SAndreas.Sandberg@ARM.com */ 1789524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1799524SAndreas.Sandberg@ARM.com 1809524SAndreas.Sandberg@ARM.com /** 1819524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1829524SAndreas.Sandberg@ARM.com * 1839524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1849524SAndreas.Sandberg@ARM.com * 1859524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1862901Ssaidi@eecs.umich.edu */ 1874762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1889524SAndreas.Sandberg@ARM.com /** @} */ 1892901Ssaidi@eecs.umich.edu 1909814Sandreas.hansson@arm.com /** 1919814Sandreas.hansson@arm.com * Get the cache line size of the system. 1929814Sandreas.hansson@arm.com */ 1939814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1949814Sandreas.hansson@arm.com 1959850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1962SN/A PCEventQueue pcEventQueue; 1979850Sandreas.hansson@arm.com#endif 1982SN/A 1992680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 20011146Smitch.hayenga@arm.com const bool multiThread; 2011806SN/A 20211005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2035713Shsul@eecs.umich.edu { 2045713Shsul@eecs.umich.edu return threadContexts[tid]; 2055713Shsul@eecs.umich.edu } 2065713Shsul@eecs.umich.edu 20712515Sgiacomo.travaglini@arm.com unsigned numContexts() const { return threadContexts.size(); } 208180SN/A 2096029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2106029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2116029Ssteve.reinhardt@amd.com int numRunningContexts(); 2126029Ssteve.reinhardt@amd.com 2138765Sgblack@eecs.umich.edu Addr pagePtr; 2148765Sgblack@eecs.umich.edu 2152378SN/A uint64_t init_param; 2162378SN/A 2172520SN/A /** Port to physical memory used for writing object files into ram at 2182520SN/A * boot.*/ 2198852Sandreas.hansson@arm.com PortProxy physProxy; 2202520SN/A 2211885SN/A /** kernel symbol table */ 2221070SN/A SymbolTable *kernelSymtab; 223954SN/A 2241070SN/A /** Object pointer for the kernel code */ 2251070SN/A ObjectFile *kernel; 2261070SN/A 22712262Sandreas.sandberg@arm.com /** Additional object files */ 22812262Sandreas.sandberg@arm.com std::vector<ObjectFile *> kernelExtras; 22912262Sandreas.sandberg@arm.com 23011838SCurtis.Dunham@arm.com /** Beginning of kernel code */ 2311070SN/A Addr kernelStart; 2321070SN/A 2331070SN/A /** End of kernel code */ 2341070SN/A Addr kernelEnd; 2351070SN/A 2361070SN/A /** Entry point in the kernel to start at */ 2371070SN/A Addr kernelEntry; 2381070SN/A 2397580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2407580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2417580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2427580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2437580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2447580SAli.Saidi@arm.com */ 2457580SAli.Saidi@arm.com Addr loadAddrMask; 2467580SAli.Saidi@arm.com 24710037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24811838SCurtis.Dunham@arm.com * This further allows more flexibility than the loadAddrMask allows alone 24911838SCurtis.Dunham@arm.com * in loading kernels and similar. The loadAddrOffset is applied after the 25010037SARM gem5 Developers * loadAddrMask. 25110037SARM gem5 Developers */ 25210037SARM gem5 Developers Addr loadAddrOffset; 25310037SARM gem5 Developers 2544997Sgblack@eecs.umich.edu public: 25511839SCurtis.Dunham@arm.com /** 25611839SCurtis.Dunham@arm.com * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 25711839SCurtis.Dunham@arm.com * if present. 25811839SCurtis.Dunham@arm.com */ 25911839SCurtis.Dunham@arm.com KvmVM* getKvmVM() { 26011839SCurtis.Dunham@arm.com return kvmVM; 26111839SCurtis.Dunham@arm.com } 26211839SCurtis.Dunham@arm.com 26312100SCurtis.Dunham@arm.com /** Verify gem5 configuration will support KVM emulation */ 26412100SCurtis.Dunham@arm.com bool validKvmEnvironment() const; 26512100SCurtis.Dunham@arm.com 2668931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2678931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2688931Sandreas.hansson@arm.com 2695795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2708931Sandreas.hansson@arm.com Addr freeMemSize() const; 2715795Ssaidi@eecs.umich.edu 2725795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2738931Sandreas.hansson@arm.com Addr memSize() const; 2748931Sandreas.hansson@arm.com 2758931Sandreas.hansson@arm.com /** 2768931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2778931Sandreas.hansson@arm.com * is part of the global address map. 2788931Sandreas.hansson@arm.com * 2798931Sandreas.hansson@arm.com * @param addr A physical address 2808931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2818931Sandreas.hansson@arm.com */ 2828931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2835795Ssaidi@eecs.umich.edu 28410467Sandreas.hansson@arm.com /** 28510467Sandreas.hansson@arm.com * Get the architecture. 28610467Sandreas.hansson@arm.com */ 28710467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 28810467Sandreas.hansson@arm.com 28910466Sandreas.hansson@arm.com /** 29010466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 29110466Sandreas.hansson@arm.com */ 29210466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 29310466Sandreas.hansson@arm.com 29410466Sandreas.hansson@arm.com /** 29511838SCurtis.Dunham@arm.com * Get the number of bits worth of in-page address for the ISA. 29610466Sandreas.hansson@arm.com */ 29710466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 29810466Sandreas.hansson@arm.com 29911420Sdavid.guillen@arm.com /** 30011420Sdavid.guillen@arm.com * The thermal model used for this system (if any). 30111420Sdavid.guillen@arm.com */ 30211420Sdavid.guillen@arm.com ThermalModel * getThermalModel() const { return thermalModel; } 30311420Sdavid.guillen@arm.com 3041885SN/A protected: 3058931Sandreas.hansson@arm.com 30611839SCurtis.Dunham@arm.com KvmVM *const kvmVM; 30711839SCurtis.Dunham@arm.com 3088931Sandreas.hansson@arm.com PhysicalMemory physmem; 3098931Sandreas.hansson@arm.com 3104762Snate@binkert.org Enums::MemoryMode memoryMode; 3119814Sandreas.hansson@arm.com 3129814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3139814Sandreas.hansson@arm.com 3147914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3157914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3168666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3177914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3187914SBrad.Beckmann@amd.com 31911838SCurtis.Dunham@arm.com /** This array is a per-system list of all devices capable of issuing a 3208832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3218832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3228832SAli.Saidi@ARM.com * like cache statistics. 3238832SAli.Saidi@ARM.com */ 32412680Sgiacomo.travaglini@arm.com std::vector<MasterInfo> masters; 3258832SAli.Saidi@ARM.com 32611420Sdavid.guillen@arm.com ThermalModel * thermalModel; 32711420Sdavid.guillen@arm.com 3287914SBrad.Beckmann@amd.com public: 3298832SAli.Saidi@ARM.com 33012680Sgiacomo.travaglini@arm.com /** 33112680Sgiacomo.travaglini@arm.com * Request an id used to create a request object in the system. All objects 3328832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3338832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 33411838SCurtis.Dunham@arm.com * regStats() phase that immediately precedes it. This allows objects in 33511838SCurtis.Dunham@arm.com * the memory system to understand how many masters may exist and 3368832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 33712680Sgiacomo.travaglini@arm.com * are finalized. 33812680Sgiacomo.travaglini@arm.com * 33912680Sgiacomo.travaglini@arm.com * Registers a MasterID: 34012680Sgiacomo.travaglini@arm.com * This method takes two parameters, one of which is optional. 34112680Sgiacomo.travaglini@arm.com * The first one is the master object, and it is compulsory; in case 34212680Sgiacomo.travaglini@arm.com * a object has multiple (sub)masters, a second parameter must be 34312680Sgiacomo.travaglini@arm.com * provided and it contains the name of the submaster. The method will 34412680Sgiacomo.travaglini@arm.com * create a master's name by concatenating the SimObject name with the 34512680Sgiacomo.travaglini@arm.com * eventual submaster string, separated by a dot. 34612680Sgiacomo.travaglini@arm.com * 34712680Sgiacomo.travaglini@arm.com * As an example: 34812680Sgiacomo.travaglini@arm.com * For a cpu having two masters: a data master and an instruction master, 34912680Sgiacomo.travaglini@arm.com * the method must be called twice: 35012680Sgiacomo.travaglini@arm.com * 35112680Sgiacomo.travaglini@arm.com * instMasterId = getMasterId(cpu, "inst"); 35212680Sgiacomo.travaglini@arm.com * dataMasterId = getMasterId(cpu, "data"); 35312680Sgiacomo.travaglini@arm.com * 35412680Sgiacomo.travaglini@arm.com * and the masters' names will be: 35512680Sgiacomo.travaglini@arm.com * - "cpu.inst" 35612680Sgiacomo.travaglini@arm.com * - "cpu.data" 35712680Sgiacomo.travaglini@arm.com * 35812680Sgiacomo.travaglini@arm.com * @param master SimObject related to the master 35912680Sgiacomo.travaglini@arm.com * @param submaster String containing the submaster's name 36012680Sgiacomo.travaglini@arm.com * @return the master's ID. 3618832SAli.Saidi@ARM.com */ 36212680Sgiacomo.travaglini@arm.com MasterID getMasterId(const SimObject* master, 36312680Sgiacomo.travaglini@arm.com std::string submaster = std::string()); 3648832SAli.Saidi@ARM.com 36512680Sgiacomo.travaglini@arm.com /** 36612680Sgiacomo.travaglini@arm.com * Registers a GLOBAL MasterID, which is a MasterID not related 36712680Sgiacomo.travaglini@arm.com * to any particular SimObject; since no SimObject is passed, 36812680Sgiacomo.travaglini@arm.com * the master gets registered by providing the full master name. 36912680Sgiacomo.travaglini@arm.com * 37012680Sgiacomo.travaglini@arm.com * @param masterName full name of the master 37112680Sgiacomo.travaglini@arm.com * @return the master's ID. 37212680Sgiacomo.travaglini@arm.com */ 37312680Sgiacomo.travaglini@arm.com MasterID getGlobalMasterId(std::string master_name); 37412680Sgiacomo.travaglini@arm.com 37512680Sgiacomo.travaglini@arm.com /** 37612680Sgiacomo.travaglini@arm.com * Get the name of an object for a given request id. 3778832SAli.Saidi@ARM.com */ 3788832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3798832SAli.Saidi@ARM.com 3808832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 38112680Sgiacomo.travaglini@arm.com MasterID maxMasters() { return masters.size(); } 38212680Sgiacomo.travaglini@arm.com 38312680Sgiacomo.travaglini@arm.com protected: 38412680Sgiacomo.travaglini@arm.com /** helper function for getMasterId */ 38512680Sgiacomo.travaglini@arm.com MasterID _getMasterId(const SimObject* master, std::string master_name); 38612680Sgiacomo.travaglini@arm.com 38712680Sgiacomo.travaglini@arm.com /** 38812680Sgiacomo.travaglini@arm.com * Helper function for constructing the full (sub)master name 38912680Sgiacomo.travaglini@arm.com * by providing the root master and the relative submaster name. 39012680Sgiacomo.travaglini@arm.com */ 39112680Sgiacomo.travaglini@arm.com std::string leafMasterName(const SimObject* master, 39212680Sgiacomo.travaglini@arm.com const std::string& submaster); 39312680Sgiacomo.travaglini@arm.com 39412680Sgiacomo.travaglini@arm.com public: 3958832SAli.Saidi@ARM.com 39611169Sandreas.hansson@arm.com void regStats() override; 3977914SBrad.Beckmann@amd.com /** 3987914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 3997914SBrad.Beckmann@amd.com * system. 4007914SBrad.Beckmann@amd.com */ 4018666SPrakash.Ramrakhyani@arm.com uint64_t 4027914SBrad.Beckmann@amd.com incWorkItemsBegin() 4037914SBrad.Beckmann@amd.com { 4047914SBrad.Beckmann@amd.com return ++workItemsBegin; 4057914SBrad.Beckmann@amd.com } 4067914SBrad.Beckmann@amd.com 4077914SBrad.Beckmann@amd.com /** 4087914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 4097914SBrad.Beckmann@amd.com * this system. 4107914SBrad.Beckmann@amd.com */ 41110037SARM gem5 Developers uint64_t 4127914SBrad.Beckmann@amd.com incWorkItemsEnd() 4137914SBrad.Beckmann@amd.com { 4147914SBrad.Beckmann@amd.com return ++workItemsEnd; 4157914SBrad.Beckmann@amd.com } 4167914SBrad.Beckmann@amd.com 4177914SBrad.Beckmann@amd.com /** 4187914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 4197914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 4207914SBrad.Beckmann@amd.com * ends. 4217914SBrad.Beckmann@amd.com */ 42210037SARM gem5 Developers int 4237914SBrad.Beckmann@amd.com markWorkItem(int index) 4247914SBrad.Beckmann@amd.com { 4257914SBrad.Beckmann@amd.com int count = 0; 4267914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 4277914SBrad.Beckmann@amd.com activeCpus[index] = true; 42810037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 4297914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 4307914SBrad.Beckmann@amd.com if (*i) count++; 4317914SBrad.Beckmann@amd.com } 4327914SBrad.Beckmann@amd.com return count; 4337914SBrad.Beckmann@amd.com } 4342901Ssaidi@eecs.umich.edu 4358666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 4368666SPrakash.Ramrakhyani@arm.com { 4378666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4388666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 4398666SPrakash.Ramrakhyani@arm.com } 4408666SPrakash.Ramrakhyani@arm.com 4418666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 4428666SPrakash.Ramrakhyani@arm.com 4431885SN/A /** 4441885SN/A * Fix up an address used to match PCs for hooking simulator 4451885SN/A * events on to target function executions. See comment in 4461885SN/A * system.cc for details. 4471885SN/A */ 4488769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 4498769Sgblack@eecs.umich.edu { 4508769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 4518769Sgblack@eecs.umich.edu } 4521885SN/A 4539645SAndreas.Sandberg@ARM.com /** @{ */ 4541885SN/A /** 4551885SN/A * Add a function-based event to the given function, to be looked 4561885SN/A * up in the specified symbol table. 4579645SAndreas.Sandberg@ARM.com * 4589645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4599645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4609645SAndreas.Sandberg@ARM.com * 4619645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4629645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4639645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4649645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4651885SN/A */ 4669645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4679645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4689645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4691885SN/A { 4709855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4711885SN/A 4729850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4731885SN/A if (symtab->findAddress(lbl, addr)) { 4749645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4759645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4761885SN/A return ev; 4771885SN/A } 4789850Sandreas.hansson@arm.com#endif 4791885SN/A 4801885SN/A return NULL; 4811885SN/A } 4821885SN/A 4831885SN/A template <class T> 4849645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 4851885SN/A { 4869645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 4871885SN/A } 4881885SN/A 4899645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4909645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 4919645SAndreas.Sandberg@ARM.com Args... args) 4929645SAndreas.Sandberg@ARM.com { 4939645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 4949645SAndreas.Sandberg@ARM.com if (!e) 4959645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 4969645SAndreas.Sandberg@ARM.com return e; 4979645SAndreas.Sandberg@ARM.com } 4989645SAndreas.Sandberg@ARM.com /** @} */ 4999645SAndreas.Sandberg@ARM.com 5009645SAndreas.Sandberg@ARM.com /** @{ */ 5019645SAndreas.Sandberg@ARM.com /** 5029645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 5039645SAndreas.Sandberg@ARM.com * 5049645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 5059645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 5069645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 5079645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 5089645SAndreas.Sandberg@ARM.com * 5099645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 5109645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 5119645SAndreas.Sandberg@ARM.com * 5129645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 5139645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 5149645SAndreas.Sandberg@ARM.com */ 5159645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 5169645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 5179645SAndreas.Sandberg@ARM.com { 5189645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 5199645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 5209645SAndreas.Sandberg@ARM.com } 5219645SAndreas.Sandberg@ARM.com 5229645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 5239645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 5249645SAndreas.Sandberg@ARM.com { 5259645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 5269645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 5279645SAndreas.Sandberg@ARM.com if (!e) 5289645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 5299645SAndreas.Sandberg@ARM.com return e; 5309645SAndreas.Sandberg@ARM.com } 5319645SAndreas.Sandberg@ARM.com /** @} */ 5329645SAndreas.Sandberg@ARM.com 53377SN/A public: 5346658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 5353960Sgblack@eecs.umich.edu bool breakpoint(); 5361070SN/A 5371070SN/A public: 5384762Snate@binkert.org typedef SystemParams Params; 5391070SN/A 5402158SN/A protected: 5412158SN/A Params *_params; 5421070SN/A 5432158SN/A public: 5441070SN/A System(Params *p); 5452SN/A ~System(); 5462SN/A 54711169Sandreas.hansson@arm.com void initState() override; 5481129SN/A 5492158SN/A const Params *params() const { return (const Params *)_params; } 5502158SN/A 5511070SN/A public: 5522378SN/A 5531070SN/A /** 55411838SCurtis.Dunham@arm.com * Returns the address the kernel starts at. 5551070SN/A * @return address the kernel starts at 5561070SN/A */ 5571070SN/A Addr getKernelStart() const { return kernelStart; } 5581070SN/A 5591070SN/A /** 56011838SCurtis.Dunham@arm.com * Returns the address the kernel ends at. 5611070SN/A * @return address the kernel ends at 5621070SN/A */ 5631070SN/A Addr getKernelEnd() const { return kernelEnd; } 5641070SN/A 5651070SN/A /** 56611838SCurtis.Dunham@arm.com * Returns the address the entry point to the kernel code. 5671070SN/A * @return entry point of the kernel code 5681070SN/A */ 5691070SN/A Addr getKernelEntry() const { return kernelEntry; } 5701070SN/A 5718601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5728601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5738601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5742378SN/A 57511005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 57611005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 57711005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5781070SN/A 57911168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 58011168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 5819342SAndreas.Sandberg@arm.com 58211168Sandreas.hansson@arm.com void drainResume() override; 5832SN/A 58477SN/A public: 5857897Shestness@cs.utexas.edu Counter totalNumInsts; 5867897Shestness@cs.utexas.edu EventQueue instEventQueue; 5878666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 5888666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 5897897Shestness@cs.utexas.edu 5902SN/A //////////////////////////////////////////// 5912SN/A // 5922SN/A // STATIC GLOBAL SYSTEM LIST 5932SN/A // 5942SN/A //////////////////////////////////////////// 5952SN/A 5962SN/A static std::vector<System *> systemList; 5972SN/A static int numSystemsRunning; 5982SN/A 5992SN/A static void printSystems(); 6002158SN/A 60111911SBrandon.Potter@amd.com FutexMap futexMap; 6029112Smarc.orr@gmail.com 60311885Sbrandon.potter@amd.com static const int maxPID = 32768; 60411885Sbrandon.potter@amd.com 60511885Sbrandon.potter@amd.com /** Process set to track which PIDs have already been allocated */ 60611885Sbrandon.potter@amd.com std::set<int> PIDs; 60711885Sbrandon.potter@amd.com 60811909SBrandon.Potter@amd.com // By convention, all signals are owned by the receiving process. The 60911909SBrandon.Potter@amd.com // receiver will delete the signal upon reception. 61011909SBrandon.Potter@amd.com std::list<BasicSignal> signalList; 61111909SBrandon.Potter@amd.com 6129292Sandreas.hansson@arm.com protected: 6139292Sandreas.hansson@arm.com 6149292Sandreas.hansson@arm.com /** 6159292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 61611838SCurtis.Dunham@arm.com * specific subclass of this system. Currently this is used by 6179292Sandreas.hansson@arm.com * Alpha and MIPS. 6189292Sandreas.hansson@arm.com * 6199292Sandreas.hansson@arm.com * @param os stream to serialize to 6209292Sandreas.hansson@arm.com */ 62110905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 6229292Sandreas.hansson@arm.com 6239292Sandreas.hansson@arm.com /** 6249292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 6259292Sandreas.hansson@arm.com * specific subclass of this system. 6269292Sandreas.hansson@arm.com * 6279292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 6289292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 6299292Sandreas.hansson@arm.com */ 63010905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 6312158SN/A 6322SN/A}; 6332SN/A 6349554Sandreas.hansson@arm.comvoid printSystems(); 6359554Sandreas.hansson@arm.com 6362SN/A#endif // __SYSTEM_HH__ 637