system.hh revision 12680
1/* 2 * Copyright (c) 2012, 2014, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Lisa Hsu 43 * Nathan Binkert 44 * Rick Strong 45 */ 46 47#ifndef __SYSTEM_HH__ 48#define __SYSTEM_HH__ 49 50#include <string> 51#include <unordered_map> 52#include <utility> 53#include <vector> 54 55#include "arch/isa_traits.hh" 56#include "base/loader/symtab.hh" 57#include "base/statistics.hh" 58#include "config/the_isa.hh" 59#include "enums/MemoryMode.hh" 60#include "mem/mem_master.hh" 61#include "mem/mem_object.hh" 62#include "mem/physical.hh" 63#include "mem/port.hh" 64#include "mem/port_proxy.hh" 65#include "params/System.hh" 66#include "sim/futex_map.hh" 67#include "sim/se_signal.hh" 68 69/** 70 * To avoid linking errors with LTO, only include the header if we 71 * actually have the definition. 72 */ 73#if THE_ISA != NULL_ISA 74#include "cpu/pc_event.hh" 75 76#endif 77 78class BaseRemoteGDB; 79class KvmVM; 80class ObjectFile; 81class ThreadContext; 82 83class System : public MemObject 84{ 85 private: 86 87 /** 88 * Private class for the system port which is only used as a 89 * master for debug access and for non-structural entities that do 90 * not have a port of their own. 91 */ 92 class SystemPort : public MasterPort 93 { 94 public: 95 96 /** 97 * Create a system port with a name and an owner. 98 */ 99 SystemPort(const std::string &_name, MemObject *_owner) 100 : MasterPort(_name, _owner) 101 { } 102 bool recvTimingResp(PacketPtr pkt) override 103 { panic("SystemPort does not receive timing!\n"); return false; } 104 void recvReqRetry() override 105 { panic("SystemPort does not expect retry!\n"); } 106 }; 107 108 SystemPort _systemPort; 109 110 public: 111 112 /** 113 * After all objects have been created and all ports are 114 * connected, check that the system port is connected. 115 */ 116 void init() override; 117 118 /** 119 * Get a reference to the system port that can be used by 120 * non-structural simulation objects like processes or threads, or 121 * external entities like loaders and debuggers, etc, to access 122 * the memory system. 123 * 124 * @return a reference to the system port we own 125 */ 126 MasterPort& getSystemPort() { return _systemPort; } 127 128 /** 129 * Additional function to return the Port of a memory object. 130 */ 131 BaseMasterPort& getMasterPort(const std::string &if_name, 132 PortID idx = InvalidPortID) override; 133 134 /** @{ */ 135 /** 136 * Is the system in atomic mode? 137 * 138 * There are currently two different atomic memory modes: 139 * 'atomic', which supports caches; and 'atomic_noncaching', which 140 * bypasses caches. The latter is used by hardware virtualized 141 * CPUs. SimObjects are expected to use Port::sendAtomic() and 142 * Port::recvAtomic() when accessing memory in this mode. 143 */ 144 bool isAtomicMode() const { 145 return memoryMode == Enums::atomic || 146 memoryMode == Enums::atomic_noncaching; 147 } 148 149 /** 150 * Is the system in timing mode? 151 * 152 * SimObjects are expected to use Port::sendTiming() and 153 * Port::recvTiming() when accessing memory in this mode. 154 */ 155 bool isTimingMode() const { 156 return memoryMode == Enums::timing; 157 } 158 159 /** 160 * Should caches be bypassed? 161 * 162 * Some CPUs need to bypass caches to allow direct memory 163 * accesses, which is required for hardware virtualization. 164 */ 165 bool bypassCaches() const { 166 return memoryMode == Enums::atomic_noncaching; 167 } 168 /** @} */ 169 170 /** @{ */ 171 /** 172 * Get the memory mode of the system. 173 * 174 * \warn This should only be used by the Python world. The C++ 175 * world should use one of the query functions above 176 * (isAtomicMode(), isTimingMode(), bypassCaches()). 177 */ 178 Enums::MemoryMode getMemoryMode() const { return memoryMode; } 179 180 /** 181 * Change the memory mode of the system. 182 * 183 * \warn This should only be called by the Python! 184 * 185 * @param mode Mode to change to (atomic/timing/...) 186 */ 187 void setMemoryMode(Enums::MemoryMode mode); 188 /** @} */ 189 190 /** 191 * Get the cache line size of the system. 192 */ 193 unsigned int cacheLineSize() const { return _cacheLineSize; } 194 195#if THE_ISA != NULL_ISA 196 PCEventQueue pcEventQueue; 197#endif 198 199 std::vector<ThreadContext *> threadContexts; 200 const bool multiThread; 201 202 ThreadContext *getThreadContext(ContextID tid) 203 { 204 return threadContexts[tid]; 205 } 206 207 unsigned numContexts() const { return threadContexts.size(); } 208 209 /** Return number of running (non-halted) thread contexts in 210 * system. These threads could be Active or Suspended. */ 211 int numRunningContexts(); 212 213 Addr pagePtr; 214 215 uint64_t init_param; 216 217 /** Port to physical memory used for writing object files into ram at 218 * boot.*/ 219 PortProxy physProxy; 220 221 /** kernel symbol table */ 222 SymbolTable *kernelSymtab; 223 224 /** Object pointer for the kernel code */ 225 ObjectFile *kernel; 226 227 /** Additional object files */ 228 std::vector<ObjectFile *> kernelExtras; 229 230 /** Beginning of kernel code */ 231 Addr kernelStart; 232 233 /** End of kernel code */ 234 Addr kernelEnd; 235 236 /** Entry point in the kernel to start at */ 237 Addr kernelEntry; 238 239 /** Mask that should be anded for binary/symbol loading. 240 * This allows one two different OS requirements for the same ISA to be 241 * handled. Some OSes are compiled for a virtual address and need to be 242 * loaded into physical memory that starts at address 0, while other 243 * bare metal tools generate images that start at address 0. 244 */ 245 Addr loadAddrMask; 246 247 /** Offset that should be used for binary/symbol loading. 248 * This further allows more flexibility than the loadAddrMask allows alone 249 * in loading kernels and similar. The loadAddrOffset is applied after the 250 * loadAddrMask. 251 */ 252 Addr loadAddrOffset; 253 254 public: 255 /** 256 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 257 * if present. 258 */ 259 KvmVM* getKvmVM() { 260 return kvmVM; 261 } 262 263 /** Verify gem5 configuration will support KVM emulation */ 264 bool validKvmEnvironment() const; 265 266 /** Get a pointer to access the physical memory of the system */ 267 PhysicalMemory& getPhysMem() { return physmem; } 268 269 /** Amount of physical memory that is still free */ 270 Addr freeMemSize() const; 271 272 /** Amount of physical memory that exists */ 273 Addr memSize() const; 274 275 /** 276 * Check if a physical address is within a range of a memory that 277 * is part of the global address map. 278 * 279 * @param addr A physical address 280 * @return Whether the address corresponds to a memory 281 */ 282 bool isMemAddr(Addr addr) const; 283 284 /** 285 * Get the architecture. 286 */ 287 Arch getArch() const { return Arch::TheISA; } 288 289 /** 290 * Get the page bytes for the ISA. 291 */ 292 Addr getPageBytes() const { return TheISA::PageBytes; } 293 294 /** 295 * Get the number of bits worth of in-page address for the ISA. 296 */ 297 Addr getPageShift() const { return TheISA::PageShift; } 298 299 /** 300 * The thermal model used for this system (if any). 301 */ 302 ThermalModel * getThermalModel() const { return thermalModel; } 303 304 protected: 305 306 KvmVM *const kvmVM; 307 308 PhysicalMemory physmem; 309 310 Enums::MemoryMode memoryMode; 311 312 const unsigned int _cacheLineSize; 313 314 uint64_t workItemsBegin; 315 uint64_t workItemsEnd; 316 uint32_t numWorkIds; 317 std::vector<bool> activeCpus; 318 319 /** This array is a per-system list of all devices capable of issuing a 320 * memory system request and an associated string for each master id. 321 * It's used to uniquely id any master in the system by name for things 322 * like cache statistics. 323 */ 324 std::vector<MasterInfo> masters; 325 326 ThermalModel * thermalModel; 327 328 public: 329 330 /** 331 * Request an id used to create a request object in the system. All objects 332 * that intend to issues requests into the memory system must request an id 333 * in the init() phase of startup. All master ids must be fixed by the 334 * regStats() phase that immediately precedes it. This allows objects in 335 * the memory system to understand how many masters may exist and 336 * appropriately name the bins of their per-master stats before the stats 337 * are finalized. 338 * 339 * Registers a MasterID: 340 * This method takes two parameters, one of which is optional. 341 * The first one is the master object, and it is compulsory; in case 342 * a object has multiple (sub)masters, a second parameter must be 343 * provided and it contains the name of the submaster. The method will 344 * create a master's name by concatenating the SimObject name with the 345 * eventual submaster string, separated by a dot. 346 * 347 * As an example: 348 * For a cpu having two masters: a data master and an instruction master, 349 * the method must be called twice: 350 * 351 * instMasterId = getMasterId(cpu, "inst"); 352 * dataMasterId = getMasterId(cpu, "data"); 353 * 354 * and the masters' names will be: 355 * - "cpu.inst" 356 * - "cpu.data" 357 * 358 * @param master SimObject related to the master 359 * @param submaster String containing the submaster's name 360 * @return the master's ID. 361 */ 362 MasterID getMasterId(const SimObject* master, 363 std::string submaster = std::string()); 364 365 /** 366 * Registers a GLOBAL MasterID, which is a MasterID not related 367 * to any particular SimObject; since no SimObject is passed, 368 * the master gets registered by providing the full master name. 369 * 370 * @param masterName full name of the master 371 * @return the master's ID. 372 */ 373 MasterID getGlobalMasterId(std::string master_name); 374 375 /** 376 * Get the name of an object for a given request id. 377 */ 378 std::string getMasterName(MasterID master_id); 379 380 /** Get the number of masters registered in the system */ 381 MasterID maxMasters() { return masters.size(); } 382 383 protected: 384 /** helper function for getMasterId */ 385 MasterID _getMasterId(const SimObject* master, std::string master_name); 386 387 /** 388 * Helper function for constructing the full (sub)master name 389 * by providing the root master and the relative submaster name. 390 */ 391 std::string leafMasterName(const SimObject* master, 392 const std::string& submaster); 393 394 public: 395 396 void regStats() override; 397 /** 398 * Called by pseudo_inst to track the number of work items started by this 399 * system. 400 */ 401 uint64_t 402 incWorkItemsBegin() 403 { 404 return ++workItemsBegin; 405 } 406 407 /** 408 * Called by pseudo_inst to track the number of work items completed by 409 * this system. 410 */ 411 uint64_t 412 incWorkItemsEnd() 413 { 414 return ++workItemsEnd; 415 } 416 417 /** 418 * Called by pseudo_inst to mark the cpus actively executing work items. 419 * Returns the total number of cpus that have executed work item begin or 420 * ends. 421 */ 422 int 423 markWorkItem(int index) 424 { 425 int count = 0; 426 assert(index < activeCpus.size()); 427 activeCpus[index] = true; 428 for (std::vector<bool>::iterator i = activeCpus.begin(); 429 i < activeCpus.end(); i++) { 430 if (*i) count++; 431 } 432 return count; 433 } 434 435 inline void workItemBegin(uint32_t tid, uint32_t workid) 436 { 437 std::pair<uint32_t,uint32_t> p(tid, workid); 438 lastWorkItemStarted[p] = curTick(); 439 } 440 441 void workItemEnd(uint32_t tid, uint32_t workid); 442 443 /** 444 * Fix up an address used to match PCs for hooking simulator 445 * events on to target function executions. See comment in 446 * system.cc for details. 447 */ 448 virtual Addr fixFuncEventAddr(Addr addr) 449 { 450 panic("Base fixFuncEventAddr not implemented.\n"); 451 } 452 453 /** @{ */ 454 /** 455 * Add a function-based event to the given function, to be looked 456 * up in the specified symbol table. 457 * 458 * The ...OrPanic flavor of the method causes the simulator to 459 * panic if the symbol can't be found. 460 * 461 * @param symtab Symbol table to use for look up. 462 * @param lbl Function to hook the event to. 463 * @param desc Description to be passed to the event. 464 * @param args Arguments to be forwarded to the event constructor. 465 */ 466 template <class T, typename... Args> 467 T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 468 const std::string &desc, Args... args) 469 { 470 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 471 472#if THE_ISA != NULL_ISA 473 if (symtab->findAddress(lbl, addr)) { 474 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 475 std::forward<Args>(args)...); 476 return ev; 477 } 478#endif 479 480 return NULL; 481 } 482 483 template <class T> 484 T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 485 { 486 return addFuncEvent<T>(symtab, lbl, lbl); 487 } 488 489 template <class T, typename... Args> 490 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 491 Args... args) 492 { 493 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 494 if (!e) 495 panic("Failed to find symbol '%s'", lbl); 496 return e; 497 } 498 /** @} */ 499 500 /** @{ */ 501 /** 502 * Add a function-based event to a kernel symbol. 503 * 504 * These functions work like their addFuncEvent() and 505 * addFuncEventOrPanic() counterparts. The only difference is that 506 * they automatically use the kernel symbol table. All arguments 507 * are forwarded to the underlying method. 508 * 509 * @see addFuncEvent() 510 * @see addFuncEventOrPanic() 511 * 512 * @param lbl Function to hook the event to. 513 * @param args Arguments to be passed to addFuncEvent 514 */ 515 template <class T, typename... Args> 516 T *addKernelFuncEvent(const char *lbl, Args... args) 517 { 518 return addFuncEvent<T>(kernelSymtab, lbl, 519 std::forward<Args>(args)...); 520 } 521 522 template <class T, typename... Args> 523 T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 524 { 525 T *e(addFuncEvent<T>(kernelSymtab, lbl, 526 std::forward<Args>(args)...)); 527 if (!e) 528 panic("Failed to find kernel symbol '%s'", lbl); 529 return e; 530 } 531 /** @} */ 532 533 public: 534 std::vector<BaseRemoteGDB *> remoteGDB; 535 bool breakpoint(); 536 537 public: 538 typedef SystemParams Params; 539 540 protected: 541 Params *_params; 542 543 public: 544 System(Params *p); 545 ~System(); 546 547 void initState() override; 548 549 const Params *params() const { return (const Params *)_params; } 550 551 public: 552 553 /** 554 * Returns the address the kernel starts at. 555 * @return address the kernel starts at 556 */ 557 Addr getKernelStart() const { return kernelStart; } 558 559 /** 560 * Returns the address the kernel ends at. 561 * @return address the kernel ends at 562 */ 563 Addr getKernelEnd() const { return kernelEnd; } 564 565 /** 566 * Returns the address the entry point to the kernel code. 567 * @return entry point of the kernel code 568 */ 569 Addr getKernelEntry() const { return kernelEntry; } 570 571 /// Allocate npages contiguous unused physical pages 572 /// @return Starting address of first page 573 Addr allocPhysPages(int npages); 574 575 ContextID registerThreadContext(ThreadContext *tc, 576 ContextID assigned = InvalidContextID); 577 void replaceThreadContext(ThreadContext *tc, ContextID context_id); 578 579 void serialize(CheckpointOut &cp) const override; 580 void unserialize(CheckpointIn &cp) override; 581 582 void drainResume() override; 583 584 public: 585 Counter totalNumInsts; 586 EventQueue instEventQueue; 587 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 588 std::map<uint32_t, Stats::Histogram*> workItemStats; 589 590 //////////////////////////////////////////// 591 // 592 // STATIC GLOBAL SYSTEM LIST 593 // 594 //////////////////////////////////////////// 595 596 static std::vector<System *> systemList; 597 static int numSystemsRunning; 598 599 static void printSystems(); 600 601 FutexMap futexMap; 602 603 static const int maxPID = 32768; 604 605 /** Process set to track which PIDs have already been allocated */ 606 std::set<int> PIDs; 607 608 // By convention, all signals are owned by the receiving process. The 609 // receiver will delete the signal upon reception. 610 std::list<BasicSignal> signalList; 611 612 protected: 613 614 /** 615 * If needed, serialize additional symbol table entries for a 616 * specific subclass of this system. Currently this is used by 617 * Alpha and MIPS. 618 * 619 * @param os stream to serialize to 620 */ 621 virtual void serializeSymtab(CheckpointOut &os) const {} 622 623 /** 624 * If needed, unserialize additional symbol table entries for a 625 * specific subclass of this system. 626 * 627 * @param cp checkpoint to unserialize from 628 * @param section relevant section in the checkpoint 629 */ 630 virtual void unserializeSymtab(CheckpointIn &cp) {} 631 632}; 633 634void printSystems(); 635 636#endif // __SYSTEM_HH__ 637