system.cc revision 11522:348411ec525a
11689SN/A/*
27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2011-2014 ARM Limited
37783SGiacomo.Gabrielli@arm.com * All rights reserved
47783SGiacomo.Gabrielli@arm.com *
57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall
67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual
77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating
87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software
97783SGiacomo.Gabrielli@arm.com * licensed hereunder.  You may use the software subject to the license
107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated
117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software,
127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form.
137783SGiacomo.Gabrielli@arm.com *
142316SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan
151689SN/A * Copyright (c) 2011 Regents of the University of California
161689SN/A * All rights reserved.
171689SN/A *
181689SN/A * Redistribution and use in source and binary forms, with or without
191689SN/A * modification, are permitted provided that the following conditions are
201689SN/A * met: redistributions of source code must retain the above copyright
211689SN/A * notice, this list of conditions and the following disclaimer;
221689SN/A * redistributions in binary form must reproduce the above copyright
231689SN/A * notice, this list of conditions and the following disclaimer in the
241689SN/A * documentation and/or other materials provided with the distribution;
251689SN/A * neither the name of the copyright holders nor the names of its
261689SN/A * contributors may be used to endorse or promote products derived from
271689SN/A * this software without specific prior written permission.
281689SN/A *
291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392665SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665SN/A *
411689SN/A * Authors: Steve Reinhardt
421061SN/A *          Lisa Hsu
435953Ssaidi@eecs.umich.edu *          Nathan Binkert
445596Sgblack@eecs.umich.edu *          Ali Saidi
451061SN/A *          Rick Strong
461061SN/A */
475596Sgblack@eecs.umich.edu
487720Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh"
495596Sgblack@eecs.umich.edu#include "arch/utility.hh"
507720Sgblack@eecs.umich.edu#include "base/loader/object_file.hh"
514637SN/A#include "base/loader/symtab.hh"
524637SN/A#include "base/str.hh"
534637SN/A#include "base/trace.hh"
544637SN/A#include "cpu/thread_context.hh"
554637SN/A#include "debug/Loader.hh"
565596Sgblack@eecs.umich.edu#include "debug/WorkItems.hh"
577720Sgblack@eecs.umich.edu#include "mem/abstract_mem.hh"
585596Sgblack@eecs.umich.edu#include "mem/physical.hh"
597720Sgblack@eecs.umich.edu#include "params/System.hh"
601061SN/A#include "sim/byteswap.hh"
612292SN/A#include "sim/debug.hh"
621061SN/A#include "sim/full_system.hh"
631061SN/A#include "sim/system.hh"
641061SN/A
655596Sgblack@eecs.umich.edu/**
661464SN/A * To avoid linking errors with LTO, only include the header if we
671061SN/A * actually have a definition.
682292SN/A */
692292SN/A#if THE_ISA != NULL_ISA
702292SN/A#include "kern/kernel_stats.hh"
712292SN/A#endif
722292SN/A
735596Sgblack@eecs.umich.eduusing namespace std;
742292SN/Ausing namespace TheISA;
751464SN/A
761464SN/Avector<System *> System::systemList;
771464SN/A
782292SN/Aint System::numSystemsRunning = 0;
793782SN/A
801464SN/ASystem::System(Params *p)
811464SN/A    : MemObject(p), _systemPort("system_port", this),
822292SN/A      _numContexts(0),
833782SN/A      multiThread(p->multi_thread),
842292SN/A      pagePtr(0),
851464SN/A      init_param(p->init_param),
867783SGiacomo.Gabrielli@arm.com      physProxy(_systemPort, p->cache_line_size),
877783SGiacomo.Gabrielli@arm.com      kernelSymtab(nullptr),
888471SGiacomo.Gabrielli@arm.com      kernel(nullptr),
898471SGiacomo.Gabrielli@arm.com      loadAddrMask(p->load_addr_mask),
908471SGiacomo.Gabrielli@arm.com      loadAddrOffset(p->load_offset),
918471SGiacomo.Gabrielli@arm.com      nextPID(0),
928471SGiacomo.Gabrielli@arm.com      physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
938471SGiacomo.Gabrielli@arm.com      memoryMode(p->mem_mode),
948471SGiacomo.Gabrielli@arm.com      _cacheLineSize(p->cache_line_size),
958471SGiacomo.Gabrielli@arm.com      workItemsBegin(0),
968471SGiacomo.Gabrielli@arm.com      workItemsEnd(0),
971061SN/A      numWorkIds(p->num_work_ids),
981061SN/A      thermalModel(p->thermal_model),
992292SN/A      _params(p),
1002292SN/A      totalNumInsts(0),
1015596Sgblack@eecs.umich.edu      instEventQueue("system instruction-based event queue")
1022292SN/A{
1032348SN/A    // add self to global system list
1042680SN/A    systemList.push_back(this);
1052348SN/A
1062680SN/A    if (FullSystem) {
1072292SN/A        kernelSymtab = new SymbolTable;
1082292SN/A        if (!debugSymbolTable)
1092292SN/A            debugSymbolTable = new SymbolTable;
1102292SN/A    }
1112292SN/A
1122292SN/A    // check if the cache line size is a value known to work
1132292SN/A    if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
1142292SN/A          _cacheLineSize == 64 || _cacheLineSize == 128))
1152292SN/A        warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
1162292SN/A
1172292SN/A    // Get the generic system master IDs
1182292SN/A    MasterID tmp_id M5_VAR_USED;
1195596Sgblack@eecs.umich.edu    tmp_id = getMasterId("writebacks");
1202292SN/A    assert(tmp_id == Request::wbMasterId);
1212348SN/A    tmp_id = getMasterId("functional");
1222680SN/A    assert(tmp_id == Request::funcMasterId);
1232348SN/A    tmp_id = getMasterId("interrupt");
1242680SN/A    assert(tmp_id == Request::intMasterId);
1252292SN/A
1262292SN/A    if (FullSystem) {
1272292SN/A        if (params()->kernel == "") {
1282292SN/A            inform("No kernel set for full system simulation. "
1292292SN/A                   "Assuming you know what you're doing\n");
1302292SN/A        } else {
1312292SN/A            // Get the kernel code
1322292SN/A            kernel = createObjectFile(params()->kernel);
1332292SN/A            inform("kernel located at: %s", params()->kernel);
1342292SN/A
1352292SN/A            if (kernel == NULL)
1362292SN/A                fatal("Could not load kernel file %s", params()->kernel);
1375596Sgblack@eecs.umich.edu
1382292SN/A            // setup entry points
1397758Sminkyu.jeong@arm.com            kernelStart = kernel->textBase();
1407758Sminkyu.jeong@arm.com            kernelEnd = kernel->bssBase() + kernel->bssSize();
1417758Sminkyu.jeong@arm.com            kernelEntry = kernel->entryPoint();
1427758Sminkyu.jeong@arm.com
1437758Sminkyu.jeong@arm.com            // load symbols
1447758Sminkyu.jeong@arm.com            if (!kernel->loadGlobalSymbols(kernelSymtab))
1457758Sminkyu.jeong@arm.com                fatal("could not load kernel symbols\n");
1462790SN/A
1472292SN/A            if (!kernel->loadLocalSymbols(kernelSymtab))
1487758Sminkyu.jeong@arm.com                fatal("could not load kernel local symbols\n");
1497758Sminkyu.jeong@arm.com
1502292SN/A            if (!kernel->loadGlobalSymbols(debugSymbolTable))
1512292SN/A                fatal("could not load kernel symbols\n");
1522292SN/A
1531858SN/A            if (!kernel->loadLocalSymbols(debugSymbolTable))
1541061SN/A                fatal("could not load kernel local symbols\n");
1555702Ssaidi@eecs.umich.edu
1565702Ssaidi@eecs.umich.edu            // Loading only needs to happen once and after memory system is
1575702Ssaidi@eecs.umich.edu            // connected so it will happen in initState()
1585702Ssaidi@eecs.umich.edu        }
1595702Ssaidi@eecs.umich.edu    }
1607720Sgblack@eecs.umich.edu
1615702Ssaidi@eecs.umich.edu    // increment the number of running systms
1625702Ssaidi@eecs.umich.edu    numSystemsRunning++;
1635702Ssaidi@eecs.umich.edu
1647720Sgblack@eecs.umich.edu    // Set back pointers to the system in all memories
1657720Sgblack@eecs.umich.edu    for (int x = 0; x < params()->memories.size(); x++)
1667720Sgblack@eecs.umich.edu        params()->memories[x]->system(this);
1677720Sgblack@eecs.umich.edu}
1685953Ssaidi@eecs.umich.edu
1695953Ssaidi@eecs.umich.eduSystem::~System()
1707720Sgblack@eecs.umich.edu{
1715953Ssaidi@eecs.umich.edu    delete kernelSymtab;
1725702Ssaidi@eecs.umich.edu    delete kernel;
1735702Ssaidi@eecs.umich.edu
1745702Ssaidi@eecs.umich.edu    for (uint32_t j = 0; j < numWorkIds; j++)
1755702Ssaidi@eecs.umich.edu        delete workItemStats[j];
1765702Ssaidi@eecs.umich.edu}
1775702Ssaidi@eecs.umich.edu
1785702Ssaidi@eecs.umich.eduvoid
1795702Ssaidi@eecs.umich.eduSystem::init()
1805702Ssaidi@eecs.umich.edu{
1815702Ssaidi@eecs.umich.edu    // check that the system port is connected
1825702Ssaidi@eecs.umich.edu    if (!_systemPort.isConnected())
1831061SN/A        panic("System port on %s is not connected.\n", name());
1845596Sgblack@eecs.umich.edu}
1851061SN/A
1867684Sgblack@eecs.umich.eduBaseMasterPort&
1871061SN/ASystem::getMasterPort(const std::string &if_name, PortID idx)
1885702Ssaidi@eecs.umich.edu{
1895702Ssaidi@eecs.umich.edu    // no need to distinguish at the moment (besides checking)
1905702Ssaidi@eecs.umich.edu    return _systemPort;
1915702Ssaidi@eecs.umich.edu}
1925702Ssaidi@eecs.umich.edu
1935702Ssaidi@eecs.umich.eduvoid
1945702Ssaidi@eecs.umich.eduSystem::setMemoryMode(Enums::MemoryMode mode)
1955702Ssaidi@eecs.umich.edu{
1965702Ssaidi@eecs.umich.edu    assert(drainState() == DrainState::Drained);
1975702Ssaidi@eecs.umich.edu    memoryMode = mode;
1981061SN/A}
1991061SN/A
2001061SN/Abool System::breakpoint()
2015596Sgblack@eecs.umich.edu{
2021061SN/A    if (remoteGDB.size())
2035556SN/A        return remoteGDB[0]->breakpoint();
2045556SN/A    return false;
2055556SN/A}
2067720Sgblack@eecs.umich.edu
2072669SN/A/**
2087720Sgblack@eecs.umich.edu * Setting rgdb_wait to a positive integer waits for a remote debugger to
2097720Sgblack@eecs.umich.edu * connect to that context ID before continuing.  This should really
2107720Sgblack@eecs.umich.edu   be a parameter on the CPU object or something...
2115556SN/A */
2121061SN/Aint rgdb_wait = -1;
2131061SN/A
2141061SN/AContextID
215System::registerThreadContext(ThreadContext *tc, ContextID assigned)
216{
217    int id;
218    if (assigned == InvalidContextID) {
219        for (id = 0; id < threadContexts.size(); id++) {
220            if (!threadContexts[id])
221                break;
222        }
223
224        if (threadContexts.size() <= id)
225            threadContexts.resize(id + 1);
226    } else {
227        if (threadContexts.size() <= assigned)
228            threadContexts.resize(assigned + 1);
229        id = assigned;
230    }
231
232    if (threadContexts[id])
233        fatal("Cannot have two CPUs with the same id (%d)\n", id);
234
235    threadContexts[id] = tc;
236    _numContexts++;
237
238#if THE_ISA != NULL_ISA
239    int port = getRemoteGDBPort();
240    if (port) {
241        RemoteGDB *rgdb = new RemoteGDB(this, tc);
242        GDBListener *gdbl = new GDBListener(rgdb, port + id);
243        gdbl->listen();
244
245        if (rgdb_wait != -1 && rgdb_wait == id)
246            gdbl->accept();
247
248        if (remoteGDB.size() <= id) {
249            remoteGDB.resize(id + 1);
250        }
251
252        remoteGDB[id] = rgdb;
253    }
254#endif
255
256    activeCpus.push_back(false);
257
258    return id;
259}
260
261int
262System::numRunningContexts()
263{
264    int running = 0;
265    for (int i = 0; i < _numContexts; ++i) {
266        if (threadContexts[i]->status() != ThreadContext::Halted)
267            ++running;
268    }
269    return running;
270}
271
272void
273System::initState()
274{
275    if (FullSystem) {
276        for (int i = 0; i < threadContexts.size(); i++)
277            TheISA::startupCPU(threadContexts[i], i);
278        // Moved from the constructor to here since it relies on the
279        // address map being resolved in the interconnect
280        /**
281         * Load the kernel code into memory
282         */
283        if (params()->kernel != "")  {
284            if (params()->kernel_addr_check) {
285                // Validate kernel mapping before loading binary
286                if (!(isMemAddr((kernelStart & loadAddrMask) +
287                                loadAddrOffset) &&
288                      isMemAddr((kernelEnd & loadAddrMask) +
289                                loadAddrOffset))) {
290                    fatal("Kernel is mapped to invalid location (not memory). "
291                          "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
292                          kernelStart,
293                          kernelEnd, (kernelStart & loadAddrMask) +
294                          loadAddrOffset,
295                          (kernelEnd & loadAddrMask) + loadAddrOffset);
296                }
297            }
298            // Load program sections into memory
299            kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset);
300
301            DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
302            DPRINTF(Loader, "Kernel end   = %#x\n", kernelEnd);
303            DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
304            DPRINTF(Loader, "Kernel loaded...\n");
305        }
306    }
307}
308
309void
310System::replaceThreadContext(ThreadContext *tc, ContextID context_id)
311{
312    if (context_id >= threadContexts.size()) {
313        panic("replaceThreadContext: bad id, %d >= %d\n",
314              context_id, threadContexts.size());
315    }
316
317    threadContexts[context_id] = tc;
318    if (context_id < remoteGDB.size())
319        remoteGDB[context_id]->replaceThreadContext(tc);
320}
321
322Addr
323System::allocPhysPages(int npages)
324{
325    Addr return_addr = pagePtr << PageShift;
326    pagePtr += npages;
327
328    Addr next_return_addr = pagePtr << PageShift;
329
330    AddrRange m5opRange(0xffff0000, 0xffffffff);
331    if (m5opRange.contains(next_return_addr)) {
332        warn("Reached m5ops MMIO region\n");
333        return_addr = 0xffffffff;
334        pagePtr = 0xffffffff >> PageShift;
335    }
336
337    if ((pagePtr << PageShift) > physmem.totalSize())
338        fatal("Out of memory, please increase size of physical memory.");
339    return return_addr;
340}
341
342Addr
343System::memSize() const
344{
345    return physmem.totalSize();
346}
347
348Addr
349System::freeMemSize() const
350{
351   return physmem.totalSize() - (pagePtr << PageShift);
352}
353
354bool
355System::isMemAddr(Addr addr) const
356{
357    return physmem.isMemAddr(addr);
358}
359
360void
361System::drainResume()
362{
363    totalNumInsts = 0;
364}
365
366void
367System::serialize(CheckpointOut &cp) const
368{
369    if (FullSystem)
370        kernelSymtab->serialize("kernel_symtab", cp);
371    SERIALIZE_SCALAR(pagePtr);
372    SERIALIZE_SCALAR(nextPID);
373    serializeSymtab(cp);
374
375    // also serialize the memories in the system
376    physmem.serializeSection(cp, "physmem");
377}
378
379
380void
381System::unserialize(CheckpointIn &cp)
382{
383    if (FullSystem)
384        kernelSymtab->unserialize("kernel_symtab", cp);
385    UNSERIALIZE_SCALAR(pagePtr);
386    UNSERIALIZE_SCALAR(nextPID);
387    unserializeSymtab(cp);
388
389    // also unserialize the memories in the system
390    physmem.unserializeSection(cp, "physmem");
391}
392
393void
394System::regStats()
395{
396    MemObject::regStats();
397
398    for (uint32_t j = 0; j < numWorkIds ; j++) {
399        workItemStats[j] = new Stats::Histogram();
400        stringstream namestr;
401        ccprintf(namestr, "work_item_type%d", j);
402        workItemStats[j]->init(20)
403                         .name(name() + "." + namestr.str())
404                         .desc("Run time stat for" + namestr.str())
405                         .prereq(*workItemStats[j]);
406    }
407}
408
409void
410System::workItemEnd(uint32_t tid, uint32_t workid)
411{
412    std::pair<uint32_t,uint32_t> p(tid, workid);
413    if (!lastWorkItemStarted.count(p))
414        return;
415
416    Tick samp = curTick() - lastWorkItemStarted[p];
417    DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
418
419    if (workid >= numWorkIds)
420        fatal("Got workid greater than specified in system configuration\n");
421
422    workItemStats[workid]->sample(samp);
423    lastWorkItemStarted.erase(p);
424}
425
426void
427System::printSystems()
428{
429    ios::fmtflags flags(cerr.flags());
430
431    vector<System *>::iterator i = systemList.begin();
432    vector<System *>::iterator end = systemList.end();
433    for (; i != end; ++i) {
434        System *sys = *i;
435        cerr << "System " << sys->name() << ": " << hex << sys << endl;
436    }
437
438    cerr.flags(flags);
439}
440
441void
442printSystems()
443{
444    System::printSystems();
445}
446
447MasterID
448System::getMasterId(std::string master_name)
449{
450    // strip off system name if the string starts with it
451    if (startswith(master_name, name()))
452        master_name = master_name.erase(0, name().size() + 1);
453
454    // CPUs in switch_cpus ask for ids again after switching
455    for (int i = 0; i < masterIds.size(); i++) {
456        if (masterIds[i] == master_name) {
457            return i;
458        }
459    }
460
461    // Verify that the statistics haven't been enabled yet
462    // Otherwise objects will have sized their stat buckets and
463    // they will be too small
464
465    if (Stats::enabled()) {
466        fatal("Can't request a masterId after regStats(). "
467                "You must do so in init().\n");
468    }
469
470    masterIds.push_back(master_name);
471
472    return masterIds.size() - 1;
473}
474
475std::string
476System::getMasterName(MasterID master_id)
477{
478    if (master_id >= masterIds.size())
479        fatal("Invalid master_id passed to getMasterName()\n");
480
481    return masterIds[master_id];
482}
483
484System *
485SystemParams::create()
486{
487    return new System(this);
488}
489