system.cc revision 8986
12689Sktlim@umich.edu/* 28703Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 482521SN/A#include "arch/isa_traits.hh" 493960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 504194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 518769Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 521070SN/A#include "base/loader/object_file.hh" 531070SN/A#include "base/loader/symtab.hh" 542521SN/A#include "base/trace.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Loader.hh" 588666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 598769Sgblack@eecs.umich.edu#include "kern/kernel_stats.hh" 602522SN/A#include "mem/physical.hh" 618769Sgblack@eecs.umich.edu#include "params/System.hh" 622037SN/A#include "sim/byteswap.hh" 638229Snate@binkert.org#include "sim/debug.hh" 648769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 6556SN/A#include "sim/system.hh" 666658Snate@binkert.org 672SN/Ausing namespace std; 682107SN/Ausing namespace TheISA; 692SN/A 702SN/Avector<System *> System::systemList; 712SN/A 722SN/Aint System::numSystemsRunning = 0; 732SN/A 741070SN/ASystem::System(Params *p) 758703Sandreas.hansson@arm.com : MemObject(p), _systemPort("system_port", this), 768703Sandreas.hansson@arm.com _numContexts(0), 778826Snilay@cs.wisc.edu pagePtr(0), 782521SN/A init_param(p->init_param), 798852Sandreas.hansson@arm.com physProxy(_systemPort), 808852Sandreas.hansson@arm.com virtProxy(_systemPort), 817580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 827770SAli.Saidi@ARM.com nextPID(0), 838931Sandreas.hansson@arm.com physmem(p->memories), 847914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 857914SBrad.Beckmann@amd.com workItemsBegin(0), 867914SBrad.Beckmann@amd.com workItemsEnd(0), 878666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 887914SBrad.Beckmann@amd.com _params(p), 898666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 907897Shestness@cs.utexas.edu instEventQueue("system instruction-based event queue") 912SN/A{ 921070SN/A // add self to global system list 931070SN/A systemList.push_back(this); 941070SN/A 958769Sgblack@eecs.umich.edu if (FullSystem) { 968769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 978769Sgblack@eecs.umich.edu if (!debugSymbolTable) 988769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 998666SPrakash.Ramrakhyani@arm.com } 1008832SAli.Saidi@ARM.com 1018832SAli.Saidi@ARM.com // Get the generic system master IDs 1028832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 1038832SAli.Saidi@ARM.com tmp_id = getMasterId("writebacks"); 1048832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 1058832SAli.Saidi@ARM.com tmp_id = getMasterId("functional"); 1068832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 1078832SAli.Saidi@ARM.com tmp_id = getMasterId("interrupt"); 1088832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1098832SAli.Saidi@ARM.com 1108885SAli.Saidi@ARM.com if (FullSystem) { 1118885SAli.Saidi@ARM.com if (params()->kernel == "") { 1128885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1138885SAli.Saidi@ARM.com "Assuming you know what you're doing if not SPARC ISA\n"); 1148885SAli.Saidi@ARM.com } else { 1158885SAli.Saidi@ARM.com // Get the kernel code 1168885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1178885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1188885SAli.Saidi@ARM.com 1198885SAli.Saidi@ARM.com if (kernel == NULL) 1208885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1218885SAli.Saidi@ARM.com 1228885SAli.Saidi@ARM.com // setup entry points 1238885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1248885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1258885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1268885SAli.Saidi@ARM.com 1278885SAli.Saidi@ARM.com // load symbols 1288885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1298885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1308885SAli.Saidi@ARM.com 1318885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1328885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1338885SAli.Saidi@ARM.com 1348885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 1358885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1368885SAli.Saidi@ARM.com 1378885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1388885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1398885SAli.Saidi@ARM.com 1408885SAli.Saidi@ARM.com // Loading only needs to happen once and after memory system is 1418885SAli.Saidi@ARM.com // connected so it will happen in initState() 1428885SAli.Saidi@ARM.com } 1438885SAli.Saidi@ARM.com } 1448885SAli.Saidi@ARM.com 1458885SAli.Saidi@ARM.com // increment the number of running systms 1468885SAli.Saidi@ARM.com numSystemsRunning++; 1478885SAli.Saidi@ARM.com 1482SN/A} 1492SN/A 1502SN/ASystem::~System() 1512SN/A{ 1521070SN/A delete kernelSymtab; 1531070SN/A delete kernel; 1548666SPrakash.Ramrakhyani@arm.com 1558666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 1568666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 1572SN/A} 1582SN/A 1598706Sandreas.hansson@arm.comvoid 1608706Sandreas.hansson@arm.comSystem::init() 1618706Sandreas.hansson@arm.com{ 1628706Sandreas.hansson@arm.com // check that the system port is connected 1638706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 1648706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 1658706Sandreas.hansson@arm.com} 1668706Sandreas.hansson@arm.com 1678922Swilliam.wang@arm.comMasterPort& 1688922Swilliam.wang@arm.comSystem::getMasterPort(const std::string &if_name, int idx) 1698703Sandreas.hansson@arm.com{ 1708703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 1718922Swilliam.wang@arm.com return _systemPort; 1728703Sandreas.hansson@arm.com} 1738703Sandreas.hansson@arm.com 1742901Ssaidi@eecs.umich.eduvoid 1754762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 1762901Ssaidi@eecs.umich.edu{ 1772901Ssaidi@eecs.umich.edu assert(getState() == Drained); 1782901Ssaidi@eecs.umich.edu memoryMode = mode; 1792901Ssaidi@eecs.umich.edu} 1802901Ssaidi@eecs.umich.edu 1813960Sgblack@eecs.umich.edubool System::breakpoint() 1823960Sgblack@eecs.umich.edu{ 1834095Sbinkertn@umich.edu if (remoteGDB.size()) 1844095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 1854095Sbinkertn@umich.edu return false; 1863960Sgblack@eecs.umich.edu} 1873960Sgblack@eecs.umich.edu 1887445Ssteve.reinhardt@amd.com/** 1897445Ssteve.reinhardt@amd.com * Setting rgdb_wait to a positive integer waits for a remote debugger to 1907445Ssteve.reinhardt@amd.com * connect to that context ID before continuing. This should really 1917445Ssteve.reinhardt@amd.com be a parameter on the CPU object or something... 1927445Ssteve.reinhardt@amd.com */ 1937445Ssteve.reinhardt@amd.comint rgdb_wait = -1; 1947445Ssteve.reinhardt@amd.com 195180SN/Aint 1965718Shsul@eecs.umich.eduSystem::registerThreadContext(ThreadContext *tc, int assigned) 1972SN/A{ 1985712Shsul@eecs.umich.edu int id; 1995718Shsul@eecs.umich.edu if (assigned == -1) { 2005718Shsul@eecs.umich.edu for (id = 0; id < threadContexts.size(); id++) { 2015718Shsul@eecs.umich.edu if (!threadContexts[id]) 2025718Shsul@eecs.umich.edu break; 2035718Shsul@eecs.umich.edu } 2045718Shsul@eecs.umich.edu 2055718Shsul@eecs.umich.edu if (threadContexts.size() <= id) 2065718Shsul@eecs.umich.edu threadContexts.resize(id + 1); 2075718Shsul@eecs.umich.edu } else { 2085718Shsul@eecs.umich.edu if (threadContexts.size() <= assigned) 2095718Shsul@eecs.umich.edu threadContexts.resize(assigned + 1); 2105718Shsul@eecs.umich.edu id = assigned; 2111806SN/A } 2121806SN/A 2132680Sktlim@umich.edu if (threadContexts[id]) 2145823Ssaidi@eecs.umich.edu fatal("Cannot have two CPUs with the same id (%d)\n", id); 2151806SN/A 2162680Sktlim@umich.edu threadContexts[id] = tc; 2175714Shsul@eecs.umich.edu _numContexts++; 2181070SN/A 2195512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 2207445Ssteve.reinhardt@amd.com if (port) { 2214095Sbinkertn@umich.edu RemoteGDB *rgdb = new RemoteGDB(this, tc); 2225512SMichael.Adler@intel.com GDBListener *gdbl = new GDBListener(rgdb, port + id); 2234095Sbinkertn@umich.edu gdbl->listen(); 2247445Ssteve.reinhardt@amd.com 2254095Sbinkertn@umich.edu if (rgdb_wait != -1 && rgdb_wait == id) 2264095Sbinkertn@umich.edu gdbl->accept(); 2271070SN/A 2284095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2294095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2304095Sbinkertn@umich.edu } 2314095Sbinkertn@umich.edu 2324095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2331070SN/A } 2341070SN/A 2357914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2367914SBrad.Beckmann@amd.com 2371806SN/A return id; 238180SN/A} 23975SN/A 2406029Ssteve.reinhardt@amd.comint 2416029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2426029Ssteve.reinhardt@amd.com{ 2436029Ssteve.reinhardt@amd.com int running = 0; 2446029Ssteve.reinhardt@amd.com for (int i = 0; i < _numContexts; ++i) { 2456029Ssteve.reinhardt@amd.com if (threadContexts[i]->status() != ThreadContext::Halted) 2466029Ssteve.reinhardt@amd.com ++running; 2476029Ssteve.reinhardt@amd.com } 2486029Ssteve.reinhardt@amd.com return running; 2496029Ssteve.reinhardt@amd.com} 2506029Ssteve.reinhardt@amd.com 251180SN/Avoid 2527733SAli.Saidi@ARM.comSystem::initState() 2531129SN/A{ 2548806Sgblack@eecs.umich.edu int i; 2558769Sgblack@eecs.umich.edu if (FullSystem) { 2568769Sgblack@eecs.umich.edu for (i = 0; i < threadContexts.size(); i++) 2578769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2588799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 2598799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 2608799Sgblack@eecs.umich.edu /** 2618799Sgblack@eecs.umich.edu * Load the kernel code into memory 2628799Sgblack@eecs.umich.edu */ 2638885SAli.Saidi@ARM.com if (params()->kernel != "") { 2648799Sgblack@eecs.umich.edu // Load program sections into memory 2658799Sgblack@eecs.umich.edu kernel->loadSections(physProxy, loadAddrMask); 2668706Sandreas.hansson@arm.com 2678799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 2688799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 2698799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 2708799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 2718799Sgblack@eecs.umich.edu } 2728706Sandreas.hansson@arm.com } 2738706Sandreas.hansson@arm.com 2748706Sandreas.hansson@arm.com activeCpus.clear(); 2758706Sandreas.hansson@arm.com 2768806Sgblack@eecs.umich.edu if (!FullSystem) 2778806Sgblack@eecs.umich.edu return; 2788806Sgblack@eecs.umich.edu 2798806Sgblack@eecs.umich.edu for (i = 0; i < threadContexts.size(); i++) 2808806Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2811129SN/A} 2821129SN/A 2831129SN/Avoid 2845713Shsul@eecs.umich.eduSystem::replaceThreadContext(ThreadContext *tc, int context_id) 285180SN/A{ 2865713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 2872680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 2885713Shsul@eecs.umich.edu context_id, threadContexts.size()); 289180SN/A } 290180SN/A 2915713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 2925713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 2935713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 2942SN/A} 2952SN/A 2962378SN/AAddr 2978601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 2982378SN/A{ 2997770SAli.Saidi@ARM.com Addr return_addr = pagePtr << LogVMPageSize; 3008601Ssteve.reinhardt@amd.com pagePtr += npages; 3018931Sandreas.hansson@arm.com if (pagePtr > physmem.totalSize()) 3023162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3032378SN/A return return_addr; 3042378SN/A} 3055795Ssaidi@eecs.umich.edu 3065795Ssaidi@eecs.umich.eduAddr 3078931Sandreas.hansson@arm.comSystem::memSize() const 3085795Ssaidi@eecs.umich.edu{ 3098931Sandreas.hansson@arm.com return physmem.totalSize(); 3105795Ssaidi@eecs.umich.edu} 3115795Ssaidi@eecs.umich.edu 3125795Ssaidi@eecs.umich.eduAddr 3138931Sandreas.hansson@arm.comSystem::freeMemSize() const 3145795Ssaidi@eecs.umich.edu{ 3158931Sandreas.hansson@arm.com return physmem.totalSize() - (pagePtr << LogVMPageSize); 3165795Ssaidi@eecs.umich.edu} 3175795Ssaidi@eecs.umich.edu 3188460SAli.Saidi@ARM.combool 3198931Sandreas.hansson@arm.comSystem::isMemAddr(Addr addr) const 3208460SAli.Saidi@ARM.com{ 3218931Sandreas.hansson@arm.com return physmem.isMemAddr(addr); 3228460SAli.Saidi@ARM.com} 3238460SAli.Saidi@ARM.com 3241070SN/Avoid 3257897Shestness@cs.utexas.eduSystem::resume() 3267897Shestness@cs.utexas.edu{ 3277897Shestness@cs.utexas.edu SimObject::resume(); 3287897Shestness@cs.utexas.edu totalNumInsts = 0; 3297897Shestness@cs.utexas.edu} 3307897Shestness@cs.utexas.edu 3317897Shestness@cs.utexas.eduvoid 3321070SN/ASystem::serialize(ostream &os) 3331070SN/A{ 3348769Sgblack@eecs.umich.edu if (FullSystem) 3358769Sgblack@eecs.umich.edu kernelSymtab->serialize("kernel_symtab", os); 3367770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 3377770SAli.Saidi@ARM.com SERIALIZE_SCALAR(nextPID); 3381070SN/A} 3391070SN/A 3401070SN/A 3411070SN/Avoid 3421070SN/ASystem::unserialize(Checkpoint *cp, const string §ion) 3431070SN/A{ 3448769Sgblack@eecs.umich.edu if (FullSystem) 3458769Sgblack@eecs.umich.edu kernelSymtab->unserialize("kernel_symtab", cp, section); 3467770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 3477770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(nextPID); 3481070SN/A} 3492SN/A 3502SN/Avoid 3518666SPrakash.Ramrakhyani@arm.comSystem::regStats() 3528666SPrakash.Ramrakhyani@arm.com{ 3538666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 3548666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 3558666SPrakash.Ramrakhyani@arm.com stringstream namestr; 3568666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 3578666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 3588666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 3598666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 3608666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 3618666SPrakash.Ramrakhyani@arm.com } 3628666SPrakash.Ramrakhyani@arm.com} 3638666SPrakash.Ramrakhyani@arm.com 3648666SPrakash.Ramrakhyani@arm.comvoid 3658666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 3668666SPrakash.Ramrakhyani@arm.com{ 3678666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3688666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 3698666SPrakash.Ramrakhyani@arm.com return; 3708666SPrakash.Ramrakhyani@arm.com 3718666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 3728666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 3738666SPrakash.Ramrakhyani@arm.com 3748666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 3758666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 3768666SPrakash.Ramrakhyani@arm.com 3778666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 3788666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 3798666SPrakash.Ramrakhyani@arm.com} 3808666SPrakash.Ramrakhyani@arm.com 3818666SPrakash.Ramrakhyani@arm.comvoid 3822SN/ASystem::printSystems() 3832SN/A{ 3842SN/A vector<System *>::iterator i = systemList.begin(); 3852SN/A vector<System *>::iterator end = systemList.end(); 3862SN/A for (; i != end; ++i) { 3872SN/A System *sys = *i; 3882SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 3892SN/A } 3902SN/A} 3912SN/A 3922SN/Avoid 3932SN/AprintSystems() 3942SN/A{ 3952SN/A System::printSystems(); 3962SN/A} 3972SN/A 3988832SAli.Saidi@ARM.comMasterID 3998832SAli.Saidi@ARM.comSystem::getMasterId(std::string master_name) 4008832SAli.Saidi@ARM.com{ 4018832SAli.Saidi@ARM.com // strip off system name if the string starts with it 4028832SAli.Saidi@ARM.com if (master_name.size() > name().size() && 4038832SAli.Saidi@ARM.com master_name.compare(0, name().size(), name()) == 0) 4048832SAli.Saidi@ARM.com master_name = master_name.erase(0, name().size() + 1); 4058832SAli.Saidi@ARM.com 4068832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 4078832SAli.Saidi@ARM.com for (int i = 0; i < masterIds.size(); i++) { 4088832SAli.Saidi@ARM.com if (masterIds[i] == master_name) { 4098832SAli.Saidi@ARM.com return i; 4108832SAli.Saidi@ARM.com } 4118832SAli.Saidi@ARM.com } 4128832SAli.Saidi@ARM.com 4138986SAli.Saidi@ARM.com // Verify that the statistics haven't been enabled yet 4148986SAli.Saidi@ARM.com // Otherwise objects will have sized their stat buckets and 4158986SAli.Saidi@ARM.com // they will be too small 4168832SAli.Saidi@ARM.com 4178986SAli.Saidi@ARM.com if (Stats::enabled()) 4188832SAli.Saidi@ARM.com fatal("Can't request a masterId after regStats(). \ 4198832SAli.Saidi@ARM.com You must do so in init().\n"); 4208832SAli.Saidi@ARM.com 4218832SAli.Saidi@ARM.com masterIds.push_back(master_name); 4228832SAli.Saidi@ARM.com 4238832SAli.Saidi@ARM.com return masterIds.size() - 1; 4248832SAli.Saidi@ARM.com} 4258832SAli.Saidi@ARM.com 4268832SAli.Saidi@ARM.comstd::string 4278832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 4288832SAli.Saidi@ARM.com{ 4298832SAli.Saidi@ARM.com if (master_id >= masterIds.size()) 4308832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 4318832SAli.Saidi@ARM.com 4328832SAli.Saidi@ARM.com return masterIds[master_id]; 4338832SAli.Saidi@ARM.com} 4348832SAli.Saidi@ARM.com 4352902Ssaidi@eecs.umich.educonst char *System::MemoryModeStrings[3] = {"invalid", "atomic", 4362902Ssaidi@eecs.umich.edu "timing"}; 4372902Ssaidi@eecs.umich.edu 4384762Snate@binkert.orgSystem * 4394762Snate@binkert.orgSystemParams::create() 4402424SN/A{ 4415530Snate@binkert.org return new System(this); 4422424SN/A} 443