system.cc revision 8832
12689Sktlim@umich.edu/* 28703Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 482521SN/A#include "arch/isa_traits.hh" 493960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 504194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 518769Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 521070SN/A#include "base/loader/object_file.hh" 531070SN/A#include "base/loader/symtab.hh" 542521SN/A#include "base/trace.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Loader.hh" 588666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 598769Sgblack@eecs.umich.edu#include "kern/kernel_stats.hh" 608799Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 612521SN/A#include "mem/mem_object.hh" 622522SN/A#include "mem/physical.hh" 638769Sgblack@eecs.umich.edu#include "params/System.hh" 642037SN/A#include "sim/byteswap.hh" 658229Snate@binkert.org#include "sim/debug.hh" 668769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 6756SN/A#include "sim/system.hh" 686658Snate@binkert.org 692SN/Ausing namespace std; 702107SN/Ausing namespace TheISA; 712SN/A 722SN/Avector<System *> System::systemList; 732SN/A 742SN/Aint System::numSystemsRunning = 0; 752SN/A 761070SN/ASystem::System(Params *p) 778703Sandreas.hansson@arm.com : MemObject(p), _systemPort("system_port", this), 788703Sandreas.hansson@arm.com physmem(p->physmem), 798703Sandreas.hansson@arm.com _numContexts(0), 808826Snilay@cs.wisc.edu pagePtr(0), 812521SN/A init_param(p->init_param), 827580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 837770SAli.Saidi@ARM.com nextPID(0), 847914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 857914SBrad.Beckmann@amd.com workItemsBegin(0), 867914SBrad.Beckmann@amd.com workItemsEnd(0), 878666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 887914SBrad.Beckmann@amd.com _params(p), 898666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 907897Shestness@cs.utexas.edu instEventQueue("system instruction-based event queue") 912SN/A{ 921070SN/A // add self to global system list 931070SN/A systemList.push_back(this); 941070SN/A 958460SAli.Saidi@ARM.com /** Keep track of all memories we can execute code out of 968460SAli.Saidi@ARM.com * in our system 978460SAli.Saidi@ARM.com */ 988460SAli.Saidi@ARM.com for (int x = 0; x < p->memories.size(); x++) { 998460SAli.Saidi@ARM.com if (!p->memories[x]) 1008460SAli.Saidi@ARM.com continue; 1018460SAli.Saidi@ARM.com memRanges.push_back(RangeSize(p->memories[x]->start(), 1028460SAli.Saidi@ARM.com p->memories[x]->size())); 1038460SAli.Saidi@ARM.com } 1048460SAli.Saidi@ARM.com 1058769Sgblack@eecs.umich.edu if (FullSystem) { 1068769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1078769Sgblack@eecs.umich.edu if (!debugSymbolTable) 1088769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 1091070SN/A 1108769Sgblack@eecs.umich.edu /** 1118799Sgblack@eecs.umich.edu * Get a port proxy to memory 1128769Sgblack@eecs.umich.edu */ 1138799Sgblack@eecs.umich.edu physProxy = new PortProxy(*getSystemPort()); 1148799Sgblack@eecs.umich.edu virtProxy = new FSTranslatingPortProxy(*getSystemPort()); 1158666SPrakash.Ramrakhyani@arm.com } 1168832SAli.Saidi@ARM.com 1178832SAli.Saidi@ARM.com // Get the generic system master IDs 1188832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 1198832SAli.Saidi@ARM.com tmp_id = getMasterId("writebacks"); 1208832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 1218832SAli.Saidi@ARM.com tmp_id = getMasterId("functional"); 1228832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 1238832SAli.Saidi@ARM.com tmp_id = getMasterId("interrupt"); 1248832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1258832SAli.Saidi@ARM.com 1262SN/A} 1272SN/A 1282SN/ASystem::~System() 1292SN/A{ 1301070SN/A delete kernelSymtab; 1311070SN/A delete kernel; 1328666SPrakash.Ramrakhyani@arm.com 1338666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 1348666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 1352SN/A} 1362SN/A 1378706Sandreas.hansson@arm.comvoid 1388706Sandreas.hansson@arm.comSystem::init() 1398706Sandreas.hansson@arm.com{ 1408706Sandreas.hansson@arm.com // check that the system port is connected 1418706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 1428706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 1438706Sandreas.hansson@arm.com} 1448706Sandreas.hansson@arm.com 1458703Sandreas.hansson@arm.comPort* 1468703Sandreas.hansson@arm.comSystem::getPort(const std::string &if_name, int idx) 1478703Sandreas.hansson@arm.com{ 1488703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 1498703Sandreas.hansson@arm.com return &_systemPort; 1508703Sandreas.hansson@arm.com} 1518703Sandreas.hansson@arm.com 1522901Ssaidi@eecs.umich.eduvoid 1534762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 1542901Ssaidi@eecs.umich.edu{ 1552901Ssaidi@eecs.umich.edu assert(getState() == Drained); 1562901Ssaidi@eecs.umich.edu memoryMode = mode; 1572901Ssaidi@eecs.umich.edu} 1582901Ssaidi@eecs.umich.edu 1593960Sgblack@eecs.umich.edubool System::breakpoint() 1603960Sgblack@eecs.umich.edu{ 1614095Sbinkertn@umich.edu if (remoteGDB.size()) 1624095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 1634095Sbinkertn@umich.edu return false; 1643960Sgblack@eecs.umich.edu} 1653960Sgblack@eecs.umich.edu 1667445Ssteve.reinhardt@amd.com/** 1677445Ssteve.reinhardt@amd.com * Setting rgdb_wait to a positive integer waits for a remote debugger to 1687445Ssteve.reinhardt@amd.com * connect to that context ID before continuing. This should really 1697445Ssteve.reinhardt@amd.com be a parameter on the CPU object or something... 1707445Ssteve.reinhardt@amd.com */ 1717445Ssteve.reinhardt@amd.comint rgdb_wait = -1; 1727445Ssteve.reinhardt@amd.com 173180SN/Aint 1745718Shsul@eecs.umich.eduSystem::registerThreadContext(ThreadContext *tc, int assigned) 1752SN/A{ 1765712Shsul@eecs.umich.edu int id; 1775718Shsul@eecs.umich.edu if (assigned == -1) { 1785718Shsul@eecs.umich.edu for (id = 0; id < threadContexts.size(); id++) { 1795718Shsul@eecs.umich.edu if (!threadContexts[id]) 1805718Shsul@eecs.umich.edu break; 1815718Shsul@eecs.umich.edu } 1825718Shsul@eecs.umich.edu 1835718Shsul@eecs.umich.edu if (threadContexts.size() <= id) 1845718Shsul@eecs.umich.edu threadContexts.resize(id + 1); 1855718Shsul@eecs.umich.edu } else { 1865718Shsul@eecs.umich.edu if (threadContexts.size() <= assigned) 1875718Shsul@eecs.umich.edu threadContexts.resize(assigned + 1); 1885718Shsul@eecs.umich.edu id = assigned; 1891806SN/A } 1901806SN/A 1912680Sktlim@umich.edu if (threadContexts[id]) 1925823Ssaidi@eecs.umich.edu fatal("Cannot have two CPUs with the same id (%d)\n", id); 1931806SN/A 1942680Sktlim@umich.edu threadContexts[id] = tc; 1955714Shsul@eecs.umich.edu _numContexts++; 1961070SN/A 1975512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 1987445Ssteve.reinhardt@amd.com if (port) { 1994095Sbinkertn@umich.edu RemoteGDB *rgdb = new RemoteGDB(this, tc); 2005512SMichael.Adler@intel.com GDBListener *gdbl = new GDBListener(rgdb, port + id); 2014095Sbinkertn@umich.edu gdbl->listen(); 2027445Ssteve.reinhardt@amd.com 2034095Sbinkertn@umich.edu if (rgdb_wait != -1 && rgdb_wait == id) 2044095Sbinkertn@umich.edu gdbl->accept(); 2051070SN/A 2064095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2074095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2084095Sbinkertn@umich.edu } 2094095Sbinkertn@umich.edu 2104095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2111070SN/A } 2121070SN/A 2137914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2147914SBrad.Beckmann@amd.com 2151806SN/A return id; 216180SN/A} 21775SN/A 2186029Ssteve.reinhardt@amd.comint 2196029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2206029Ssteve.reinhardt@amd.com{ 2216029Ssteve.reinhardt@amd.com int running = 0; 2226029Ssteve.reinhardt@amd.com for (int i = 0; i < _numContexts; ++i) { 2236029Ssteve.reinhardt@amd.com if (threadContexts[i]->status() != ThreadContext::Halted) 2246029Ssteve.reinhardt@amd.com ++running; 2256029Ssteve.reinhardt@amd.com } 2266029Ssteve.reinhardt@amd.com return running; 2276029Ssteve.reinhardt@amd.com} 2286029Ssteve.reinhardt@amd.com 229180SN/Avoid 2307733SAli.Saidi@ARM.comSystem::initState() 2311129SN/A{ 2328806Sgblack@eecs.umich.edu int i; 2338769Sgblack@eecs.umich.edu if (FullSystem) { 2348769Sgblack@eecs.umich.edu for (i = 0; i < threadContexts.size(); i++) 2358769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2368799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 2378799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 2388799Sgblack@eecs.umich.edu /** 2398799Sgblack@eecs.umich.edu * Load the kernel code into memory 2408799Sgblack@eecs.umich.edu */ 2418799Sgblack@eecs.umich.edu if (params()->kernel == "") { 2428799Sgblack@eecs.umich.edu inform("No kernel set for full system simulation. " 2438799Sgblack@eecs.umich.edu "Assuming you know what you're doing...\n"); 2448799Sgblack@eecs.umich.edu } else { 2458799Sgblack@eecs.umich.edu // Load kernel code 2468799Sgblack@eecs.umich.edu kernel = createObjectFile(params()->kernel); 2478799Sgblack@eecs.umich.edu inform("kernel located at: %s", params()->kernel); 2488706Sandreas.hansson@arm.com 2498799Sgblack@eecs.umich.edu if (kernel == NULL) 2508799Sgblack@eecs.umich.edu fatal("Could not load kernel file %s", params()->kernel); 2518706Sandreas.hansson@arm.com 2528799Sgblack@eecs.umich.edu // Load program sections into memory 2538799Sgblack@eecs.umich.edu kernel->loadSections(physProxy, loadAddrMask); 2548706Sandreas.hansson@arm.com 2558799Sgblack@eecs.umich.edu // setup entry points 2568799Sgblack@eecs.umich.edu kernelStart = kernel->textBase(); 2578799Sgblack@eecs.umich.edu kernelEnd = kernel->bssBase() + kernel->bssSize(); 2588799Sgblack@eecs.umich.edu kernelEntry = kernel->entryPoint(); 2598706Sandreas.hansson@arm.com 2608799Sgblack@eecs.umich.edu // load symbols 2618799Sgblack@eecs.umich.edu if (!kernel->loadGlobalSymbols(kernelSymtab)) 2628799Sgblack@eecs.umich.edu fatal("could not load kernel symbols\n"); 2638706Sandreas.hansson@arm.com 2648799Sgblack@eecs.umich.edu if (!kernel->loadLocalSymbols(kernelSymtab)) 2658799Sgblack@eecs.umich.edu fatal("could not load kernel local symbols\n"); 2668706Sandreas.hansson@arm.com 2678799Sgblack@eecs.umich.edu if (!kernel->loadGlobalSymbols(debugSymbolTable)) 2688799Sgblack@eecs.umich.edu fatal("could not load kernel symbols\n"); 2698706Sandreas.hansson@arm.com 2708799Sgblack@eecs.umich.edu if (!kernel->loadLocalSymbols(debugSymbolTable)) 2718799Sgblack@eecs.umich.edu fatal("could not load kernel local symbols\n"); 2728706Sandreas.hansson@arm.com 2738799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 2748799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 2758799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 2768799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 2778799Sgblack@eecs.umich.edu } 2788706Sandreas.hansson@arm.com } 2798706Sandreas.hansson@arm.com 2808706Sandreas.hansson@arm.com // increment the number of running systms 2818706Sandreas.hansson@arm.com numSystemsRunning++; 2828706Sandreas.hansson@arm.com 2838706Sandreas.hansson@arm.com activeCpus.clear(); 2848706Sandreas.hansson@arm.com 2858806Sgblack@eecs.umich.edu if (!FullSystem) 2868806Sgblack@eecs.umich.edu return; 2878806Sgblack@eecs.umich.edu 2888806Sgblack@eecs.umich.edu for (i = 0; i < threadContexts.size(); i++) 2898806Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2901129SN/A} 2911129SN/A 2921129SN/Avoid 2935713Shsul@eecs.umich.eduSystem::replaceThreadContext(ThreadContext *tc, int context_id) 294180SN/A{ 2955713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 2962680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 2975713Shsul@eecs.umich.edu context_id, threadContexts.size()); 298180SN/A } 299180SN/A 3005713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 3015713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 3025713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 3032SN/A} 3042SN/A 3052378SN/AAddr 3068601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 3072378SN/A{ 3087770SAli.Saidi@ARM.com Addr return_addr = pagePtr << LogVMPageSize; 3098601Ssteve.reinhardt@amd.com pagePtr += npages; 3108813Sgblack@eecs.umich.edu if (pagePtr > physmem->size()) 3113162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3122378SN/A return return_addr; 3132378SN/A} 3145795Ssaidi@eecs.umich.edu 3155795Ssaidi@eecs.umich.eduAddr 3165795Ssaidi@eecs.umich.eduSystem::memSize() 3175795Ssaidi@eecs.umich.edu{ 3185795Ssaidi@eecs.umich.edu return physmem->size(); 3195795Ssaidi@eecs.umich.edu} 3205795Ssaidi@eecs.umich.edu 3215795Ssaidi@eecs.umich.eduAddr 3225795Ssaidi@eecs.umich.eduSystem::freeMemSize() 3235795Ssaidi@eecs.umich.edu{ 3247770SAli.Saidi@ARM.com return physmem->size() - (pagePtr << LogVMPageSize); 3255795Ssaidi@eecs.umich.edu} 3265795Ssaidi@eecs.umich.edu 3278460SAli.Saidi@ARM.combool 3288460SAli.Saidi@ARM.comSystem::isMemory(const Addr addr) const 3298460SAli.Saidi@ARM.com{ 3308460SAli.Saidi@ARM.com std::list<Range<Addr> >::const_iterator i; 3318460SAli.Saidi@ARM.com for (i = memRanges.begin(); i != memRanges.end(); i++) { 3328460SAli.Saidi@ARM.com if (*i == addr) 3338460SAli.Saidi@ARM.com return true; 3348460SAli.Saidi@ARM.com } 3358460SAli.Saidi@ARM.com return false; 3368460SAli.Saidi@ARM.com} 3378460SAli.Saidi@ARM.com 3381070SN/Avoid 3397897Shestness@cs.utexas.eduSystem::resume() 3407897Shestness@cs.utexas.edu{ 3417897Shestness@cs.utexas.edu SimObject::resume(); 3427897Shestness@cs.utexas.edu totalNumInsts = 0; 3437897Shestness@cs.utexas.edu} 3447897Shestness@cs.utexas.edu 3457897Shestness@cs.utexas.eduvoid 3461070SN/ASystem::serialize(ostream &os) 3471070SN/A{ 3488769Sgblack@eecs.umich.edu if (FullSystem) 3498769Sgblack@eecs.umich.edu kernelSymtab->serialize("kernel_symtab", os); 3507770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 3517770SAli.Saidi@ARM.com SERIALIZE_SCALAR(nextPID); 3521070SN/A} 3531070SN/A 3541070SN/A 3551070SN/Avoid 3561070SN/ASystem::unserialize(Checkpoint *cp, const string §ion) 3571070SN/A{ 3588769Sgblack@eecs.umich.edu if (FullSystem) 3598769Sgblack@eecs.umich.edu kernelSymtab->unserialize("kernel_symtab", cp, section); 3607770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 3617770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(nextPID); 3621070SN/A} 3632SN/A 3642SN/Avoid 3658666SPrakash.Ramrakhyani@arm.comSystem::regStats() 3668666SPrakash.Ramrakhyani@arm.com{ 3678666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 3688666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 3698666SPrakash.Ramrakhyani@arm.com stringstream namestr; 3708666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 3718666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 3728666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 3738666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 3748666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 3758666SPrakash.Ramrakhyani@arm.com } 3768666SPrakash.Ramrakhyani@arm.com} 3778666SPrakash.Ramrakhyani@arm.com 3788666SPrakash.Ramrakhyani@arm.comvoid 3798666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 3808666SPrakash.Ramrakhyani@arm.com{ 3818666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 3828666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 3838666SPrakash.Ramrakhyani@arm.com return; 3848666SPrakash.Ramrakhyani@arm.com 3858666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 3868666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 3878666SPrakash.Ramrakhyani@arm.com 3888666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 3898666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 3908666SPrakash.Ramrakhyani@arm.com 3918666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 3928666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 3938666SPrakash.Ramrakhyani@arm.com} 3948666SPrakash.Ramrakhyani@arm.com 3958666SPrakash.Ramrakhyani@arm.comvoid 3962SN/ASystem::printSystems() 3972SN/A{ 3982SN/A vector<System *>::iterator i = systemList.begin(); 3992SN/A vector<System *>::iterator end = systemList.end(); 4002SN/A for (; i != end; ++i) { 4012SN/A System *sys = *i; 4022SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 4032SN/A } 4042SN/A} 4052SN/A 4062SN/Avoid 4072SN/AprintSystems() 4082SN/A{ 4092SN/A System::printSystems(); 4102SN/A} 4112SN/A 4128832SAli.Saidi@ARM.comMasterID 4138832SAli.Saidi@ARM.comSystem::getMasterId(std::string master_name) 4148832SAli.Saidi@ARM.com{ 4158832SAli.Saidi@ARM.com // strip off system name if the string starts with it 4168832SAli.Saidi@ARM.com if (master_name.size() > name().size() && 4178832SAli.Saidi@ARM.com master_name.compare(0, name().size(), name()) == 0) 4188832SAli.Saidi@ARM.com master_name = master_name.erase(0, name().size() + 1); 4198832SAli.Saidi@ARM.com 4208832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 4218832SAli.Saidi@ARM.com for (int i = 0; i < masterIds.size(); i++) { 4228832SAli.Saidi@ARM.com if (masterIds[i] == master_name) { 4238832SAli.Saidi@ARM.com return i; 4248832SAli.Saidi@ARM.com } 4258832SAli.Saidi@ARM.com } 4268832SAli.Saidi@ARM.com 4278832SAli.Saidi@ARM.com // todo: Check if stats are enabled yet 4288832SAli.Saidi@ARM.com // I just don't know a good way to do it 4298832SAli.Saidi@ARM.com 4308832SAli.Saidi@ARM.com if (false) 4318832SAli.Saidi@ARM.com fatal("Can't request a masterId after regStats(). \ 4328832SAli.Saidi@ARM.com You must do so in init().\n"); 4338832SAli.Saidi@ARM.com 4348832SAli.Saidi@ARM.com masterIds.push_back(master_name); 4358832SAli.Saidi@ARM.com 4368832SAli.Saidi@ARM.com return masterIds.size() - 1; 4378832SAli.Saidi@ARM.com} 4388832SAli.Saidi@ARM.com 4398832SAli.Saidi@ARM.comstd::string 4408832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 4418832SAli.Saidi@ARM.com{ 4428832SAli.Saidi@ARM.com if (master_id >= masterIds.size()) 4438832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 4448832SAli.Saidi@ARM.com 4458832SAli.Saidi@ARM.com return masterIds[master_id]; 4468832SAli.Saidi@ARM.com} 4478832SAli.Saidi@ARM.com 4482902Ssaidi@eecs.umich.educonst char *System::MemoryModeStrings[3] = {"invalid", "atomic", 4492902Ssaidi@eecs.umich.edu "timing"}; 4502902Ssaidi@eecs.umich.edu 4514762Snate@binkert.orgSystem * 4524762Snate@binkert.orgSystemParams::create() 4532424SN/A{ 4545530Snate@binkert.org return new System(this); 4552424SN/A} 456