system.cc revision 56
112SN/A/* 210037SARM gem5 Developers * Copyright (c) 2003 The Regents of The University of Michigan 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 1512SN/A * 1612SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712SN/A */ 2812SN/A 2912SN/A#include "cpu/exec_context.hh" 3012SN/A#include "base/loader/object_file.hh" 3112SN/A#include "mem/functional_mem/memory_control.hh" 3212SN/A#include "mem/functional_mem/physical_memory.hh" 3312SN/A#include "base/loader/symtab.hh" 3412SN/A#include "base/remote_gdb.hh" 3512SN/A#include "targetarch/vtophys.hh" 3612SN/A#include "sim/system.hh" 3712SN/A#include "base/trace.hh" 3812SN/A 392665Ssaidi@eecs.umich.eduusing namespace std; 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.eduvector<System *> System::systemList; 4212SN/A 4312SN/Aint System::numSystemsRunning = 0; 445616Snate@binkert.org 4512SN/ASystem::System(const std::string _name, 4612SN/A MemoryController *_memCtrl, 4756SN/A PhysicalMemory *_physmem, 484484Sbinkertn@umich.edu const std::string &kernel_path, 498229Snate@binkert.org const std::string &console_path, 502439SN/A const std::string &palcode, 517676Snate@binkert.org const std::string &boot_osflags) 528232Snate@binkert.org : SimObject(_name), 532423SN/A kernel_panic_event(&pcEventQueue, "kernel panic"), 548229Snate@binkert.org console_panic_event(&pcEventQueue, "console panic"), 552423SN/A badaddr_event(&pcEventQueue, "badaddr"), 5612SN/A skip_power_state(&pcEventQueue, "tl_v48_capture_power_state"), 5712SN/A skip_scavenge_boot(&pcEventQueue, "pmap_scavenge_boot"), 5812SN/A printf_event(&pcEventQueue, "printf"), 5910880SCurtis.Dunham@arm.com debug_printf_event(&pcEventQueue, "debug_printf", false), 6012SN/A debug_printfr_event(&pcEventQueue, "debug_printfr", true), 61443SN/A dump_mbuf_event(&pcEventQueue, "dump_mbuf"), 62443SN/A memCtrl(_memCtrl), 632207SN/A physmem(_physmem), 642207SN/A remoteGDB(NULL), 65443SN/A gdbListen(NULL) 66468SN/A{ 671708SN/A kernelSymtab = new SymbolTable; 681708SN/A consoleSymtab = new SymbolTable; 69443SN/A 70468SN/A ObjectFile *kernel = createObjectFile(kernel_path); 71443SN/A if (kernel == NULL) 72443SN/A fatal("Could not load kernel file %s", kernel_path); 73443SN/A 74468SN/A ObjectFile *console = createObjectFile(console_path); 7510037SARM gem5 Developers if (console == NULL) 76443SN/A fatal("Could not load console file %s", console_path); 77443SN/A 78443SN/A if (!kernel->loadGlobalSymbols(kernelSymtab)) 792476SN/A panic("could not load kernel symbols\n"); 802207SN/A 812207SN/A if (!console->loadGlobalSymbols(consoleSymtab)) 822207SN/A panic("could not load console symbols\n"); 832207SN/A 842207SN/A // Load pal file 854111Sgblack@eecs.umich.edu ObjectFile *pal = createObjectFile(palcode); 864111Sgblack@eecs.umich.edu if (pal == NULL) 872620SN/A fatal("Could not load PALcode file %s", palcode); 884111Sgblack@eecs.umich.edu pal->loadSections(physmem, true); 894111Sgblack@eecs.umich.edu 904111Sgblack@eecs.umich.edu // copy of initial reg file contents 914111Sgblack@eecs.umich.edu initRegs = new RegFile; 924111Sgblack@eecs.umich.edu memset(initRegs, 0, sizeof(RegFile)); 932207SN/A 942207SN/A // Load console file 955383Sgblack@eecs.umich.edu console->loadSections(physmem, true); 965383Sgblack@eecs.umich.edu 975383Sgblack@eecs.umich.edu // Load kernel file 985383Sgblack@eecs.umich.edu kernel->loadSections(physmem, true); 995383Sgblack@eecs.umich.edu kernelStart = kernel->textBase(); 1005383Sgblack@eecs.umich.edu kernelEnd = kernel->bssBase() + kernel->bssSize(); 1015383Sgblack@eecs.umich.edu kernelEntry = kernel->entryPoint(); 1024166Sgblack@eecs.umich.edu 1034166Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n" 1045874Sgblack@eecs.umich.edu "Kernel end = %#x\n" 1055874Sgblack@eecs.umich.edu "Kernel entry = %#x\n", 1065874Sgblack@eecs.umich.edu kernelStart, kernelEnd, kernelEntry); 1075874Sgblack@eecs.umich.edu 10810037SARM gem5 Developers // Setup kernel boot parameters 10910037SARM gem5 Developers initRegs->pc = 0x4001; 1107095Sgblack@eecs.umich.edu initRegs->npc = initRegs->pc + sizeof(MachInst); 1117095Sgblack@eecs.umich.edu 1127095Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 1137095Sgblack@eecs.umich.edu 1147095Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 11510037SARM gem5 Developers Addr addr = 0; 11610037SARM gem5 Developers 11710037SARM gem5 Developers for(int i = 0; i < 12/*MAX_CPUS*/; i++) 11810037SARM gem5 Developers xc_array[i] = (ExecContext *) 0; 11910037SARM gem5 Developers 1206691Stjones1@inf.ed.ac.uk num_cpus = 0; 1216691Stjones1@inf.ed.ac.uk 12210037SARM gem5 Developers if (kernelSymtab->findAddress("enable_async_printf", addr)) { 12310037SARM gem5 Developers Addr paddr = vtophys(physmem, addr); 12410037SARM gem5 Developers uint8_t *enable_async_printf = 12510037SARM gem5 Developers physmem->dma_addr(paddr, sizeof(uint32_t)); 1266691Stjones1@inf.ed.ac.uk 1276691Stjones1@inf.ed.ac.uk if (enable_async_printf) 12810037SARM gem5 Developers *(uint32_t *)enable_async_printf = 0; 1296691Stjones1@inf.ed.ac.uk } 1306691Stjones1@inf.ed.ac.uk 1316691Stjones1@inf.ed.ac.uk if (consoleSymtab->findAddress("env_booted_osflags", addr)) { 1326691Stjones1@inf.ed.ac.uk Addr paddr = vtophys(physmem, addr); 1332207SN/A char *osflags = (char *)physmem->dma_addr(paddr, sizeof(uint32_t)); 1342600SN/A 1352207SN/A if (osflags) 1362207SN/A strcpy(osflags, boot_osflags.c_str()); 1372207SN/A } 1382207SN/A 13910037SARM gem5 Developers if (kernelSymtab->findAddress("panic", addr)) 1402207SN/A kernel_panic_event.schedule(addr); 1412207SN/A else 1422207SN/A panic("could not find kernel symbol \'panic\'"); 1432207SN/A 1442207SN/A if (consoleSymtab->findAddress("panic", addr)) 1452238SN/A console_panic_event.schedule(addr); 1462207SN/A 1472207SN/A if (kernelSymtab->findAddress("badaddr", addr)) 1482238SN/A badaddr_event.schedule(addr); 1496392Ssaidi@eecs.umich.edu else 1506392Ssaidi@eecs.umich.edu panic("could not find kernel symbol \'badaddr\'"); 1516392Ssaidi@eecs.umich.edu 15210810Sbr@bsdpad.com if (kernelSymtab->findAddress("tl_v48_capture_power_state", addr)) 15310810Sbr@bsdpad.com skip_power_state.schedule(addr); 15410810Sbr@bsdpad.com 1552207SN/A if (kernelSymtab->findAddress("pmap_scavenge_boot", addr)) 1562207SN/A skip_scavenge_boot.schedule(addr); 1572207SN/A 1582207SN/A#if TRACING_ON 1592238SN/A if (kernelSymtab->findAddress("printf", addr)) 1602238SN/A printf_event.schedule(addr); 1612600SN/A 1622238SN/A if (kernelSymtab->findAddress("m5printf", addr)) 1632238SN/A debug_printf_event.schedule(addr); 1642238SN/A 16510810Sbr@bsdpad.com if (kernelSymtab->findAddress("m5printfr", addr)) 16610810Sbr@bsdpad.com debug_printfr_event.schedule(addr); 1672238SN/A 1682238SN/A if (kernelSymtab->findAddress("m5_dump_mbuf", addr)) 1692238SN/A dump_mbuf_event.schedule(addr); 1702238SN/A#endif 1712238SN/A 1722238SN/A#endif 1732600SN/A 1742238SN/A // add self to global system list 1752238SN/A systemList.push_back(this); 1762238SN/A 1772238SN/A numSystemsRunning++; 1782238SN/A} 1792238SN/A 1802238SN/A 1812238SN/ASystem::~System() 1822238SN/A{ 1832238SN/A delete kernelSymtab; 1842238SN/A delete consoleSymtab; 1852238SN/A delete initRegs; 1862238SN/A} 1872238SN/A 1882238SN/A 1892238SN/Avoid 1902238SN/ASystem::initBootContext(ExecContext *xc) 1912238SN/A{ 1922238SN/A xc->regs = *initRegs; 1932238SN/A 1942238SN/A remoteGDB = new RemoteGDB(this, xc); 1952238SN/A gdbListen = new GDBListener(remoteGDB, 7000); 1962600SN/A gdbListen->listen(); 1972600SN/A 1982600SN/A // Reset the system 1992600SN/A // 20010810Sbr@bsdpad.com TheISA::init(physmem, &xc->regs); 20110810Sbr@bsdpad.com} 20210810Sbr@bsdpad.com 20310810Sbr@bsdpad.com 20410810Sbr@bsdpad.comvoid 20510810Sbr@bsdpad.comSystem::registerExecContext(ExecContext *xc) 20610810Sbr@bsdpad.com{ 20710810Sbr@bsdpad.com if (num_cpus == 12/*MAX_CPUS*/) 20810810Sbr@bsdpad.com panic("Too many CPU's\n"); 20910810Sbr@bsdpad.com xc_array[xc->cpu_id] = xc; 2102600SN/A num_cpus++; 2112238SN/A} 2122238SN/A 2132238SN/A 2142472SN/Avoid 21510880SCurtis.Dunham@arm.comSystem::printSystems() 2162976Sgblack@eecs.umich.edu{ 2172976Sgblack@eecs.umich.edu vector<System *>::iterator i = systemList.begin(); 2182976Sgblack@eecs.umich.edu vector<System *>::iterator end = systemList.end(); 2192976Sgblack@eecs.umich.edu for (; i != end; ++i) { 2202976Sgblack@eecs.umich.edu System *sys = *i; 2212976Sgblack@eecs.umich.edu cerr << "System " << sys->name() << ": " << hex << sys << endl; 2222976Sgblack@eecs.umich.edu } 2232976Sgblack@eecs.umich.edu} 2242976Sgblack@eecs.umich.edu 2252976Sgblack@eecs.umich.edu 2262976Sgblack@eecs.umich.eduextern "C" 2272976Sgblack@eecs.umich.eduvoid 2282976Sgblack@eecs.umich.eduprintSystems() 2292976Sgblack@eecs.umich.edu{ 2302976Sgblack@eecs.umich.edu System::printSystems(); 2312976Sgblack@eecs.umich.edu} 2322976Sgblack@eecs.umich.edu 2332976Sgblack@eecs.umich.edu 2342976Sgblack@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(System) 2352976Sgblack@eecs.umich.edu 23610037SARM gem5 Developers SimObjectParam<MemoryController *> mem_ctl; 23710037SARM gem5 Developers SimObjectParam<PhysicalMemory *> physmem; 2382976Sgblack@eecs.umich.edu 2392976Sgblack@eecs.umich.edu Param<string> kernel_code; 2402976Sgblack@eecs.umich.edu Param<string> console_code; 2412976Sgblack@eecs.umich.edu Param<string> pal_code; 2422976Sgblack@eecs.umich.edu Param<string> boot_osflags; 2432976Sgblack@eecs.umich.edu 2442976Sgblack@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(System) 2452976Sgblack@eecs.umich.edu 2462238SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(System) 2472976Sgblack@eecs.umich.edu 24812SN/A INIT_PARAM(mem_ctl, "memory controller"), 24912SN/A INIT_PARAM(physmem, "phsyical memory"), 25012SN/A INIT_PARAM(kernel_code, "file that contains the kernel code"), 25112SN/A INIT_PARAM(console_code, "file that contains the console code"), 25210880SCurtis.Dunham@arm.com INIT_PARAM(pal_code, "file that contains palcode"), 253360SN/A INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", 25410880SCurtis.Dunham@arm.com "a") 25510360Sandreas.hansson@arm.com 256443SN/AEND_INIT_SIM_OBJECT_PARAMS(System) 25712SN/A 258443SN/A 259443SN/ACREATE_SIM_OBJECT(System) 26012SN/A{ 261468SN/A System *sys = new System(getInstanceName(), mem_ctl, physmem, 2621708SN/A kernel_code, console_code, pal_code, 2631708SN/A boot_osflags); 26412SN/A 265468SN/A return sys; 266443SN/A} 267443SN/A 26812SN/AREGISTER_SIM_OBJECT("System", System) 269468SN/A