system.cc revision 13644
12689Sktlim@umich.edu/* 212680Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2014,2017-2018 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 4811793Sbrandon.potter@amd.com#include "sim/system.hh" 4911793Sbrandon.potter@amd.com 5012515Sgiacomo.travaglini@arm.com#include <algorithm> 5112515Sgiacomo.travaglini@arm.com 523960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 534194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 541070SN/A#include "base/loader/object_file.hh" 551070SN/A#include "base/loader/symtab.hh" 569142Ssteve.reinhardt@amd.com#include "base/str.hh" 572521SN/A#include "base/trace.hh" 5811839SCurtis.Dunham@arm.com#include "config/use_kvm.hh" 5911839SCurtis.Dunham@arm.com#if USE_KVM 6012100SCurtis.Dunham@arm.com#include "cpu/kvm/base.hh" 6111839SCurtis.Dunham@arm.com#include "cpu/kvm/vm.hh" 6211839SCurtis.Dunham@arm.com#endif 6312122Sjose.marinho@arm.com#include "cpu/base.hh" 648229Snate@binkert.org#include "cpu/thread_context.hh" 658232Snate@binkert.org#include "debug/Loader.hh" 668666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 679293Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 682522SN/A#include "mem/physical.hh" 698769Sgblack@eecs.umich.edu#include "params/System.hh" 702037SN/A#include "sim/byteswap.hh" 718229Snate@binkert.org#include "sim/debug.hh" 728769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 736658Snate@binkert.org 7410494Sandreas.hansson@arm.com/** 7510494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7610494Sandreas.hansson@arm.com * actually have a definition. 7710494Sandreas.hansson@arm.com */ 7810494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7910494Sandreas.hansson@arm.com#include "kern/kernel_stats.hh" 8011793Sbrandon.potter@amd.com 8110494Sandreas.hansson@arm.com#endif 8210494Sandreas.hansson@arm.com 832SN/Ausing namespace std; 842107SN/Ausing namespace TheISA; 852SN/A 862SN/Avector<System *> System::systemList; 872SN/A 882SN/Aint System::numSystemsRunning = 0; 892SN/A 901070SN/ASystem::System(Params *p) 918703Sandreas.hansson@arm.com : MemObject(p), _systemPort("system_port", this), 9211146Smitch.hayenga@arm.com multiThread(p->multi_thread), 938826Snilay@cs.wisc.edu pagePtr(0), 942521SN/A init_param(p->init_param), 959814Sandreas.hansson@arm.com physProxy(_systemPort, p->cache_line_size), 9610360Sandreas.hansson@arm.com kernelSymtab(nullptr), 9710360Sandreas.hansson@arm.com kernel(nullptr), 987580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 9910037SARM gem5 Developers loadAddrOffset(p->load_offset), 10011839SCurtis.Dunham@arm.com#if USE_KVM 10111839SCurtis.Dunham@arm.com kvmVM(p->kvm_vm), 10211839SCurtis.Dunham@arm.com#else 10311839SCurtis.Dunham@arm.com kvmVM(nullptr), 10411839SCurtis.Dunham@arm.com#endif 10510700Sandreas.hansson@arm.com physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve), 1067914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 1079814Sandreas.hansson@arm.com _cacheLineSize(p->cache_line_size), 1087914SBrad.Beckmann@amd.com workItemsBegin(0), 1097914SBrad.Beckmann@amd.com workItemsEnd(0), 1108666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 11111420Sdavid.guillen@arm.com thermalModel(p->thermal_model), 1127914SBrad.Beckmann@amd.com _params(p), 1138666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 1147897Shestness@cs.utexas.edu instEventQueue("system instruction-based event queue") 1152SN/A{ 1161070SN/A // add self to global system list 1171070SN/A systemList.push_back(this); 1181070SN/A 11911839SCurtis.Dunham@arm.com#if USE_KVM 12011839SCurtis.Dunham@arm.com if (kvmVM) { 12111839SCurtis.Dunham@arm.com kvmVM->setSystem(this); 12211839SCurtis.Dunham@arm.com } 12311839SCurtis.Dunham@arm.com#endif 12411839SCurtis.Dunham@arm.com 1258769Sgblack@eecs.umich.edu if (FullSystem) { 1268769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1278769Sgblack@eecs.umich.edu if (!debugSymbolTable) 1288769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 1298666SPrakash.Ramrakhyani@arm.com } 1308832SAli.Saidi@ARM.com 1319814Sandreas.hansson@arm.com // check if the cache line size is a value known to work 1329814Sandreas.hansson@arm.com if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 1339814Sandreas.hansson@arm.com _cacheLineSize == 64 || _cacheLineSize == 128)) 1349814Sandreas.hansson@arm.com warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 1359814Sandreas.hansson@arm.com 1368832SAli.Saidi@ARM.com // Get the generic system master IDs 1378832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 13812680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "writebacks"); 1398832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 14012680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "functional"); 1418832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 14212680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "interrupt"); 1438832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1448832SAli.Saidi@ARM.com 1458885SAli.Saidi@ARM.com if (FullSystem) { 1468885SAli.Saidi@ARM.com if (params()->kernel == "") { 1478885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1489147Snilay@cs.wisc.edu "Assuming you know what you're doing\n"); 1498885SAli.Saidi@ARM.com } else { 1508885SAli.Saidi@ARM.com // Get the kernel code 1518885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1528885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1538885SAli.Saidi@ARM.com 1548885SAli.Saidi@ARM.com if (kernel == NULL) 1558885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1568885SAli.Saidi@ARM.com 1578885SAli.Saidi@ARM.com // setup entry points 1588885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1598885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1608885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1618885SAli.Saidi@ARM.com 16212272SGeoffrey.Blake@arm.com // If load_addr_mask is set to 0x0, then auto-calculate 16312272SGeoffrey.Blake@arm.com // the smallest mask to cover all kernel addresses so gem5 16412272SGeoffrey.Blake@arm.com // can relocate the kernel to a new offset. 16512272SGeoffrey.Blake@arm.com if (loadAddrMask == 0) { 16612272SGeoffrey.Blake@arm.com Addr shift_amt = findMsbSet(kernelEnd - kernelStart) + 1; 16712272SGeoffrey.Blake@arm.com loadAddrMask = ((Addr)1 << shift_amt) - 1; 16812272SGeoffrey.Blake@arm.com } 16912272SGeoffrey.Blake@arm.com 1708885SAli.Saidi@ARM.com // load symbols 1718885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1728885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1738885SAli.Saidi@ARM.com 1748885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1758885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1768885SAli.Saidi@ARM.com 1778885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 1788885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1798885SAli.Saidi@ARM.com 1808885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1818885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1828885SAli.Saidi@ARM.com 1838885SAli.Saidi@ARM.com // Loading only needs to happen once and after memory system is 1848885SAli.Saidi@ARM.com // connected so it will happen in initState() 1858885SAli.Saidi@ARM.com } 18612262Sandreas.sandberg@arm.com 18712262Sandreas.sandberg@arm.com for (const auto &obj_name : p->kernel_extras) { 18812262Sandreas.sandberg@arm.com inform("Loading additional kernel object: %s", obj_name); 18912262Sandreas.sandberg@arm.com ObjectFile *obj = createObjectFile(obj_name); 19012262Sandreas.sandberg@arm.com fatal_if(!obj, "Failed to additional kernel object '%s'.\n", 19112262Sandreas.sandberg@arm.com obj_name); 19212262Sandreas.sandberg@arm.com kernelExtras.push_back(obj); 19312262Sandreas.sandberg@arm.com } 1948885SAli.Saidi@ARM.com } 1958885SAli.Saidi@ARM.com 19611838SCurtis.Dunham@arm.com // increment the number of running systems 1978885SAli.Saidi@ARM.com numSystemsRunning++; 1988885SAli.Saidi@ARM.com 1999053Sdam.sunwoo@arm.com // Set back pointers to the system in all memories 2009053Sdam.sunwoo@arm.com for (int x = 0; x < params()->memories.size(); x++) 2019053Sdam.sunwoo@arm.com params()->memories[x]->system(this); 2022SN/A} 2032SN/A 2042SN/ASystem::~System() 2052SN/A{ 2061070SN/A delete kernelSymtab; 2071070SN/A delete kernel; 2088666SPrakash.Ramrakhyani@arm.com 2098666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 2108666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 2112SN/A} 2122SN/A 2138706Sandreas.hansson@arm.comvoid 2148706Sandreas.hansson@arm.comSystem::init() 2158706Sandreas.hansson@arm.com{ 2168706Sandreas.hansson@arm.com // check that the system port is connected 2178706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 2188706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 2198706Sandreas.hansson@arm.com} 2208706Sandreas.hansson@arm.com 2219294Sandreas.hansson@arm.comBaseMasterPort& 2229294Sandreas.hansson@arm.comSystem::getMasterPort(const std::string &if_name, PortID idx) 2238703Sandreas.hansson@arm.com{ 2248703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 2258922Swilliam.wang@arm.com return _systemPort; 2268703Sandreas.hansson@arm.com} 2278703Sandreas.hansson@arm.com 2282901Ssaidi@eecs.umich.eduvoid 2294762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 2302901Ssaidi@eecs.umich.edu{ 23110913Sandreas.sandberg@arm.com assert(drainState() == DrainState::Drained); 2322901Ssaidi@eecs.umich.edu memoryMode = mode; 2332901Ssaidi@eecs.umich.edu} 2342901Ssaidi@eecs.umich.edu 2353960Sgblack@eecs.umich.edubool System::breakpoint() 2363960Sgblack@eecs.umich.edu{ 2374095Sbinkertn@umich.edu if (remoteGDB.size()) 2384095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 2394095Sbinkertn@umich.edu return false; 2403960Sgblack@eecs.umich.edu} 2413960Sgblack@eecs.umich.edu 24211005Sandreas.sandberg@arm.comContextID 24311005Sandreas.sandberg@arm.comSystem::registerThreadContext(ThreadContext *tc, ContextID assigned) 2442SN/A{ 24512443Sgabeblack@google.com int id = assigned; 24612443Sgabeblack@google.com if (id == InvalidContextID) { 24712443Sgabeblack@google.com // Find an unused context ID for this thread. 24812443Sgabeblack@google.com id = 0; 24912443Sgabeblack@google.com while (id < threadContexts.size() && threadContexts[id]) 25012443Sgabeblack@google.com id++; 2511806SN/A } 2521806SN/A 25312443Sgabeblack@google.com if (threadContexts.size() <= id) 25412443Sgabeblack@google.com threadContexts.resize(id + 1); 25512443Sgabeblack@google.com 25612443Sgabeblack@google.com fatal_if(threadContexts[id], 25712443Sgabeblack@google.com "Cannot have two CPUs with the same id (%d)\n", id); 2581806SN/A 2592680Sktlim@umich.edu threadContexts[id] = tc; 2601070SN/A 2619850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 2625512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 2637445Ssteve.reinhardt@amd.com if (port) { 26412449Sgabeblack@google.com RemoteGDB *rgdb = new RemoteGDB(this, tc, port + id); 26512449Sgabeblack@google.com rgdb->listen(); 2667445Ssteve.reinhardt@amd.com 26712122Sjose.marinho@arm.com BaseCPU *cpu = tc->getCpuPtr(); 26812122Sjose.marinho@arm.com if (cpu->waitForRemoteGDB()) { 26912122Sjose.marinho@arm.com inform("%s: Waiting for a remote GDB connection on port %d.\n", 27012449Sgabeblack@google.com cpu->name(), rgdb->port()); 27112122Sjose.marinho@arm.com 27212449Sgabeblack@google.com rgdb->connect(); 27312122Sjose.marinho@arm.com } 2744095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2754095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2764095Sbinkertn@umich.edu } 2774095Sbinkertn@umich.edu 2784095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2791070SN/A } 2809850Sandreas.hansson@arm.com#endif 2811070SN/A 2827914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2837914SBrad.Beckmann@amd.com 2841806SN/A return id; 285180SN/A} 28675SN/A 2876029Ssteve.reinhardt@amd.comint 2886029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2896029Ssteve.reinhardt@amd.com{ 29012515Sgiacomo.travaglini@arm.com return std::count_if( 29112515Sgiacomo.travaglini@arm.com threadContexts.cbegin(), 29212515Sgiacomo.travaglini@arm.com threadContexts.cend(), 29312515Sgiacomo.travaglini@arm.com [] (ThreadContext* tc) { 29413644Sqtt2@cornell.edu return ((tc->status() != ThreadContext::Halted) && 29513644Sqtt2@cornell.edu (tc->status() != ThreadContext::Halting)); 29612515Sgiacomo.travaglini@arm.com } 29712515Sgiacomo.travaglini@arm.com ); 2986029Ssteve.reinhardt@amd.com} 2996029Ssteve.reinhardt@amd.com 300180SN/Avoid 3017733SAli.Saidi@ARM.comSystem::initState() 3021129SN/A{ 3038769Sgblack@eecs.umich.edu if (FullSystem) { 3049172Snilay@cs.wisc.edu for (int i = 0; i < threadContexts.size(); i++) 3058769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 3068799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 3078799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 3088799Sgblack@eecs.umich.edu /** 3098799Sgblack@eecs.umich.edu * Load the kernel code into memory 3108799Sgblack@eecs.umich.edu */ 3118885SAli.Saidi@ARM.com if (params()->kernel != "") { 31210282Sdam.sunwoo@arm.com if (params()->kernel_addr_check) { 31310282Sdam.sunwoo@arm.com // Validate kernel mapping before loading binary 31410282Sdam.sunwoo@arm.com if (!(isMemAddr((kernelStart & loadAddrMask) + 31510282Sdam.sunwoo@arm.com loadAddrOffset) && 31610282Sdam.sunwoo@arm.com isMemAddr((kernelEnd & loadAddrMask) + 31710282Sdam.sunwoo@arm.com loadAddrOffset))) { 31810282Sdam.sunwoo@arm.com fatal("Kernel is mapped to invalid location (not memory). " 31910282Sdam.sunwoo@arm.com "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n", 32010282Sdam.sunwoo@arm.com kernelStart, 32110282Sdam.sunwoo@arm.com kernelEnd, (kernelStart & loadAddrMask) + 32210282Sdam.sunwoo@arm.com loadAddrOffset, 32310282Sdam.sunwoo@arm.com (kernelEnd & loadAddrMask) + loadAddrOffset); 32410282Sdam.sunwoo@arm.com } 3259187SKrishnendra.Nathella@arm.com } 3268799Sgblack@eecs.umich.edu // Load program sections into memory 32710037SARM gem5 Developers kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset); 32812262Sandreas.sandberg@arm.com for (const auto &extra_kernel : kernelExtras) { 32912262Sandreas.sandberg@arm.com extra_kernel->loadSections(physProxy, loadAddrMask, 33012262Sandreas.sandberg@arm.com loadAddrOffset); 33112262Sandreas.sandberg@arm.com } 3328706Sandreas.hansson@arm.com 3338799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 3348799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 3358799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 3368799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 3378799Sgblack@eecs.umich.edu } 3388706Sandreas.hansson@arm.com } 3391129SN/A} 3401129SN/A 3411129SN/Avoid 34211005Sandreas.sandberg@arm.comSystem::replaceThreadContext(ThreadContext *tc, ContextID context_id) 343180SN/A{ 3445713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 3452680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 3465713Shsul@eecs.umich.edu context_id, threadContexts.size()); 347180SN/A } 348180SN/A 3495713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 3505713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 3515713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 3522SN/A} 3532SN/A 35412100SCurtis.Dunham@arm.combool 35512100SCurtis.Dunham@arm.comSystem::validKvmEnvironment() const 35612100SCurtis.Dunham@arm.com{ 35712100SCurtis.Dunham@arm.com#if USE_KVM 35812100SCurtis.Dunham@arm.com if (threadContexts.empty()) 35912100SCurtis.Dunham@arm.com return false; 36012100SCurtis.Dunham@arm.com 36112100SCurtis.Dunham@arm.com for (auto tc : threadContexts) { 36212100SCurtis.Dunham@arm.com if (dynamic_cast<BaseKvmCPU*>(tc->getCpuPtr()) == nullptr) { 36312100SCurtis.Dunham@arm.com return false; 36412100SCurtis.Dunham@arm.com } 36512100SCurtis.Dunham@arm.com } 36612100SCurtis.Dunham@arm.com return true; 36712100SCurtis.Dunham@arm.com#else 36812100SCurtis.Dunham@arm.com return false; 36912100SCurtis.Dunham@arm.com#endif 37012100SCurtis.Dunham@arm.com} 37112100SCurtis.Dunham@arm.com 3722378SN/AAddr 3738601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 3742378SN/A{ 37510318Sandreas.hansson@arm.com Addr return_addr = pagePtr << PageShift; 3768601Ssteve.reinhardt@amd.com pagePtr += npages; 37710553Salexandru.dutu@amd.com 37810553Salexandru.dutu@amd.com Addr next_return_addr = pagePtr << PageShift; 37910553Salexandru.dutu@amd.com 38010553Salexandru.dutu@amd.com AddrRange m5opRange(0xffff0000, 0xffffffff); 38110553Salexandru.dutu@amd.com if (m5opRange.contains(next_return_addr)) { 38210553Salexandru.dutu@amd.com warn("Reached m5ops MMIO region\n"); 38310553Salexandru.dutu@amd.com return_addr = 0xffffffff; 38410553Salexandru.dutu@amd.com pagePtr = 0xffffffff >> PageShift; 38510553Salexandru.dutu@amd.com } 38610553Salexandru.dutu@amd.com 38710318Sandreas.hansson@arm.com if ((pagePtr << PageShift) > physmem.totalSize()) 3883162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3892378SN/A return return_addr; 3902378SN/A} 3915795Ssaidi@eecs.umich.edu 3925795Ssaidi@eecs.umich.eduAddr 3938931Sandreas.hansson@arm.comSystem::memSize() const 3945795Ssaidi@eecs.umich.edu{ 3958931Sandreas.hansson@arm.com return physmem.totalSize(); 3965795Ssaidi@eecs.umich.edu} 3975795Ssaidi@eecs.umich.edu 3985795Ssaidi@eecs.umich.eduAddr 3998931Sandreas.hansson@arm.comSystem::freeMemSize() const 4005795Ssaidi@eecs.umich.edu{ 40110318Sandreas.hansson@arm.com return physmem.totalSize() - (pagePtr << PageShift); 4025795Ssaidi@eecs.umich.edu} 4035795Ssaidi@eecs.umich.edu 4048460SAli.Saidi@ARM.combool 4058931Sandreas.hansson@arm.comSystem::isMemAddr(Addr addr) const 4068460SAli.Saidi@ARM.com{ 4078931Sandreas.hansson@arm.com return physmem.isMemAddr(addr); 4088460SAli.Saidi@ARM.com} 4098460SAli.Saidi@ARM.com 4101070SN/Avoid 4119342SAndreas.Sandberg@arm.comSystem::drainResume() 4127897Shestness@cs.utexas.edu{ 4137897Shestness@cs.utexas.edu totalNumInsts = 0; 4147897Shestness@cs.utexas.edu} 4157897Shestness@cs.utexas.edu 4167897Shestness@cs.utexas.eduvoid 41710905Sandreas.sandberg@arm.comSystem::serialize(CheckpointOut &cp) const 4181070SN/A{ 4198769Sgblack@eecs.umich.edu if (FullSystem) 42010905Sandreas.sandberg@arm.com kernelSymtab->serialize("kernel_symtab", cp); 4217770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 42210905Sandreas.sandberg@arm.com serializeSymtab(cp); 4239293Sandreas.hansson@arm.com 4249293Sandreas.hansson@arm.com // also serialize the memories in the system 42510905Sandreas.sandberg@arm.com physmem.serializeSection(cp, "physmem"); 4261070SN/A} 4271070SN/A 4281070SN/A 4291070SN/Avoid 43010905Sandreas.sandberg@arm.comSystem::unserialize(CheckpointIn &cp) 4311070SN/A{ 4328769Sgblack@eecs.umich.edu if (FullSystem) 43310905Sandreas.sandberg@arm.com kernelSymtab->unserialize("kernel_symtab", cp); 4347770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 43510905Sandreas.sandberg@arm.com unserializeSymtab(cp); 4369293Sandreas.hansson@arm.com 4379293Sandreas.hansson@arm.com // also unserialize the memories in the system 43810905Sandreas.sandberg@arm.com physmem.unserializeSection(cp, "physmem"); 4391070SN/A} 4402SN/A 4412SN/Avoid 4428666SPrakash.Ramrakhyani@arm.comSystem::regStats() 4438666SPrakash.Ramrakhyani@arm.com{ 44411522Sstephan.diestelhorst@arm.com MemObject::regStats(); 44511522Sstephan.diestelhorst@arm.com 4468666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 4478666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 4488666SPrakash.Ramrakhyani@arm.com stringstream namestr; 4498666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 4508666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 4518666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 4528666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 4538666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 4548666SPrakash.Ramrakhyani@arm.com } 4558666SPrakash.Ramrakhyani@arm.com} 4568666SPrakash.Ramrakhyani@arm.com 4578666SPrakash.Ramrakhyani@arm.comvoid 4588666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 4598666SPrakash.Ramrakhyani@arm.com{ 4608666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4618666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 4628666SPrakash.Ramrakhyani@arm.com return; 4638666SPrakash.Ramrakhyani@arm.com 4648666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 4658666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 4668666SPrakash.Ramrakhyani@arm.com 4678666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 4688666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 4698666SPrakash.Ramrakhyani@arm.com 4708666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 4718666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 4728666SPrakash.Ramrakhyani@arm.com} 4738666SPrakash.Ramrakhyani@arm.com 4748666SPrakash.Ramrakhyani@arm.comvoid 4752SN/ASystem::printSystems() 4762SN/A{ 47710375Sandreas.hansson@arm.com ios::fmtflags flags(cerr.flags()); 47810375Sandreas.hansson@arm.com 4792SN/A vector<System *>::iterator i = systemList.begin(); 4802SN/A vector<System *>::iterator end = systemList.end(); 4812SN/A for (; i != end; ++i) { 4822SN/A System *sys = *i; 4832SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 4842SN/A } 48510375Sandreas.hansson@arm.com 48610375Sandreas.hansson@arm.com cerr.flags(flags); 4872SN/A} 4882SN/A 4892SN/Avoid 4902SN/AprintSystems() 4912SN/A{ 4922SN/A System::printSystems(); 4932SN/A} 4942SN/A 49512965Sgiacomo.travaglini@arm.comstd::string 49612965Sgiacomo.travaglini@arm.comSystem::stripSystemName(const std::string& master_name) const 49712965Sgiacomo.travaglini@arm.com{ 49812965Sgiacomo.travaglini@arm.com if (startswith(master_name, name())) { 49912965Sgiacomo.travaglini@arm.com return master_name.substr(name().size()); 50012965Sgiacomo.travaglini@arm.com } else { 50112965Sgiacomo.travaglini@arm.com return master_name; 50212965Sgiacomo.travaglini@arm.com } 50312965Sgiacomo.travaglini@arm.com} 50412965Sgiacomo.travaglini@arm.com 5058832SAli.Saidi@ARM.comMasterID 50612965Sgiacomo.travaglini@arm.comSystem::lookupMasterId(const SimObject* obj) const 50712965Sgiacomo.travaglini@arm.com{ 50812965Sgiacomo.travaglini@arm.com MasterID id = Request::invldMasterId; 50912965Sgiacomo.travaglini@arm.com 51012965Sgiacomo.travaglini@arm.com // number of occurrences of the SimObject pointer 51112965Sgiacomo.travaglini@arm.com // in the master list. 51212965Sgiacomo.travaglini@arm.com auto obj_number = 0; 51312965Sgiacomo.travaglini@arm.com 51412965Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 51512965Sgiacomo.travaglini@arm.com if (masters[i].obj == obj) { 51612965Sgiacomo.travaglini@arm.com id = i; 51712965Sgiacomo.travaglini@arm.com obj_number++; 51812965Sgiacomo.travaglini@arm.com } 51912965Sgiacomo.travaglini@arm.com } 52012965Sgiacomo.travaglini@arm.com 52112965Sgiacomo.travaglini@arm.com fatal_if(obj_number > 1, 52212965Sgiacomo.travaglini@arm.com "Cannot lookup MasterID by SimObject pointer: " 52312965Sgiacomo.travaglini@arm.com "More than one master is sharing the same SimObject\n"); 52412965Sgiacomo.travaglini@arm.com 52512965Sgiacomo.travaglini@arm.com return id; 52612965Sgiacomo.travaglini@arm.com} 52712965Sgiacomo.travaglini@arm.com 52812965Sgiacomo.travaglini@arm.comMasterID 52912965Sgiacomo.travaglini@arm.comSystem::lookupMasterId(const std::string& master_name) const 53012965Sgiacomo.travaglini@arm.com{ 53112965Sgiacomo.travaglini@arm.com std::string name = stripSystemName(master_name); 53212965Sgiacomo.travaglini@arm.com 53312965Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 53412965Sgiacomo.travaglini@arm.com if (masters[i].masterName == name) { 53512965Sgiacomo.travaglini@arm.com return i; 53612965Sgiacomo.travaglini@arm.com } 53712965Sgiacomo.travaglini@arm.com } 53812965Sgiacomo.travaglini@arm.com 53912965Sgiacomo.travaglini@arm.com return Request::invldMasterId; 54012965Sgiacomo.travaglini@arm.com} 54112965Sgiacomo.travaglini@arm.com 54212965Sgiacomo.travaglini@arm.comMasterID 54312965Sgiacomo.travaglini@arm.comSystem::getGlobalMasterId(const std::string& master_name) 5448832SAli.Saidi@ARM.com{ 54512680Sgiacomo.travaglini@arm.com return _getMasterId(nullptr, master_name); 54612680Sgiacomo.travaglini@arm.com} 54712680Sgiacomo.travaglini@arm.com 54812680Sgiacomo.travaglini@arm.comMasterID 54912680Sgiacomo.travaglini@arm.comSystem::getMasterId(const SimObject* master, std::string submaster) 55012680Sgiacomo.travaglini@arm.com{ 55112680Sgiacomo.travaglini@arm.com auto master_name = leafMasterName(master, submaster); 55212680Sgiacomo.travaglini@arm.com return _getMasterId(master, master_name); 55312680Sgiacomo.travaglini@arm.com} 55412680Sgiacomo.travaglini@arm.com 55512680Sgiacomo.travaglini@arm.comMasterID 55612965Sgiacomo.travaglini@arm.comSystem::_getMasterId(const SimObject* master, const std::string& master_name) 55712680Sgiacomo.travaglini@arm.com{ 55812965Sgiacomo.travaglini@arm.com std::string name = stripSystemName(master_name); 5598832SAli.Saidi@ARM.com 5608832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 56112680Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 56212965Sgiacomo.travaglini@arm.com if (masters[i].masterName == name) { 5638832SAli.Saidi@ARM.com return i; 5648832SAli.Saidi@ARM.com } 5658832SAli.Saidi@ARM.com } 5668832SAli.Saidi@ARM.com 5678986SAli.Saidi@ARM.com // Verify that the statistics haven't been enabled yet 5688986SAli.Saidi@ARM.com // Otherwise objects will have sized their stat buckets and 5698986SAli.Saidi@ARM.com // they will be too small 5708832SAli.Saidi@ARM.com 57110367SAndrew.Bardsley@arm.com if (Stats::enabled()) { 57210367SAndrew.Bardsley@arm.com fatal("Can't request a masterId after regStats(). " 57310367SAndrew.Bardsley@arm.com "You must do so in init().\n"); 57410367SAndrew.Bardsley@arm.com } 5758832SAli.Saidi@ARM.com 57612680Sgiacomo.travaglini@arm.com // Generate a new MasterID incrementally 57712680Sgiacomo.travaglini@arm.com MasterID master_id = masters.size(); 5788832SAli.Saidi@ARM.com 57912680Sgiacomo.travaglini@arm.com // Append the new Master metadata to the group of system Masters. 58012965Sgiacomo.travaglini@arm.com masters.emplace_back(master, name, master_id); 58112680Sgiacomo.travaglini@arm.com 58212680Sgiacomo.travaglini@arm.com return masters.back().masterId; 58312680Sgiacomo.travaglini@arm.com} 58412680Sgiacomo.travaglini@arm.com 58512680Sgiacomo.travaglini@arm.comstd::string 58612680Sgiacomo.travaglini@arm.comSystem::leafMasterName(const SimObject* master, const std::string& submaster) 58712680Sgiacomo.travaglini@arm.com{ 58812694Sgiacomo.travaglini@arm.com if (submaster.empty()) { 58912694Sgiacomo.travaglini@arm.com return master->name(); 59012694Sgiacomo.travaglini@arm.com } else { 59112694Sgiacomo.travaglini@arm.com // Get the full master name by appending the submaster name to 59212694Sgiacomo.travaglini@arm.com // the root SimObject master name 59312694Sgiacomo.travaglini@arm.com return master->name() + "." + submaster; 59412694Sgiacomo.travaglini@arm.com } 5958832SAli.Saidi@ARM.com} 5968832SAli.Saidi@ARM.com 5978832SAli.Saidi@ARM.comstd::string 5988832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 5998832SAli.Saidi@ARM.com{ 60012680Sgiacomo.travaglini@arm.com if (master_id >= masters.size()) 6018832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 6028832SAli.Saidi@ARM.com 60312680Sgiacomo.travaglini@arm.com const auto& master_info = masters[master_id]; 60412680Sgiacomo.travaglini@arm.com return master_info.masterName; 6058832SAli.Saidi@ARM.com} 6068832SAli.Saidi@ARM.com 6074762Snate@binkert.orgSystem * 6084762Snate@binkert.orgSystemParams::create() 6092424SN/A{ 6105530Snate@binkert.org return new System(this); 6112424SN/A} 612