system.cc revision 12694
12689Sktlim@umich.edu/* 210282Sdam.sunwoo@arm.com * Copyright (c) 2011-2014,2017-2018 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 4811793Sbrandon.potter@amd.com#include "sim/system.hh" 4911793Sbrandon.potter@amd.com 503960Sgblack@eecs.umich.edu#include <algorithm> 514194Ssaidi@eecs.umich.edu 521070SN/A#include "arch/remote_gdb.hh" 531070SN/A#include "arch/utility.hh" 549142Ssteve.reinhardt@amd.com#include "base/loader/object_file.hh" 552521SN/A#include "base/loader/symtab.hh" 5611839SCurtis.Dunham@arm.com#include "base/str.hh" 5711839SCurtis.Dunham@arm.com#include "base/trace.hh" 5812100SCurtis.Dunham@arm.com#include "config/use_kvm.hh" 5911839SCurtis.Dunham@arm.com#if USE_KVM 6011839SCurtis.Dunham@arm.com#include "cpu/kvm/base.hh" 618229Snate@binkert.org#include "cpu/kvm/vm.hh" 628232Snate@binkert.org#endif 638666SPrakash.Ramrakhyani@arm.com#include "cpu/base.hh" 649293Sandreas.hansson@arm.com#include "cpu/thread_context.hh" 652522SN/A#include "debug/Loader.hh" 668769Sgblack@eecs.umich.edu#include "debug/WorkItems.hh" 672037SN/A#include "mem/abstract_mem.hh" 688229Snate@binkert.org#include "mem/physical.hh" 698769Sgblack@eecs.umich.edu#include "params/System.hh" 706658Snate@binkert.org#include "sim/byteswap.hh" 7110494Sandreas.hansson@arm.com#include "sim/debug.hh" 7210494Sandreas.hansson@arm.com#include "sim/full_system.hh" 7310494Sandreas.hansson@arm.com 7410494Sandreas.hansson@arm.com/** 7510494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7610494Sandreas.hansson@arm.com * actually have a definition. 7711793Sbrandon.potter@amd.com */ 7810494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7910494Sandreas.hansson@arm.com#include "kern/kernel_stats.hh" 802SN/A 812107SN/A#endif 822SN/A 832SN/Ausing namespace std; 842SN/Ausing namespace TheISA; 852SN/A 862SN/Avector<System *> System::systemList; 871070SN/A 888703Sandreas.hansson@arm.comint System::numSystemsRunning = 0; 898703Sandreas.hansson@arm.com 9011146Smitch.hayenga@arm.comSystem::System(Params *p) 918826Snilay@cs.wisc.edu : MemObject(p), _systemPort("system_port", this), 922521SN/A multiThread(p->multi_thread), 939814Sandreas.hansson@arm.com pagePtr(0), 9410360Sandreas.hansson@arm.com init_param(p->init_param), 9510360Sandreas.hansson@arm.com physProxy(_systemPort, p->cache_line_size), 967580SAli.Saidi@arm.com kernelSymtab(nullptr), 9710037SARM gem5 Developers kernel(nullptr), 9811839SCurtis.Dunham@arm.com loadAddrMask(p->load_addr_mask), 9911839SCurtis.Dunham@arm.com loadAddrOffset(p->load_offset), 10011839SCurtis.Dunham@arm.com#if USE_KVM 10111839SCurtis.Dunham@arm.com kvmVM(p->kvm_vm), 10211839SCurtis.Dunham@arm.com#else 10310700Sandreas.hansson@arm.com kvmVM(nullptr), 1047914SBrad.Beckmann@amd.com#endif 1059814Sandreas.hansson@arm.com physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve), 1067914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 1077914SBrad.Beckmann@amd.com _cacheLineSize(p->cache_line_size), 1088666SPrakash.Ramrakhyani@arm.com workItemsBegin(0), 10911420Sdavid.guillen@arm.com workItemsEnd(0), 1107914SBrad.Beckmann@amd.com numWorkIds(p->num_work_ids), 1118666SPrakash.Ramrakhyani@arm.com thermalModel(p->thermal_model), 1127897Shestness@cs.utexas.edu _params(p), 1132SN/A totalNumInsts(0), 1141070SN/A instEventQueue("system instruction-based event queue") 1151070SN/A{ 1161070SN/A // add self to global system list 11711839SCurtis.Dunham@arm.com systemList.push_back(this); 11811839SCurtis.Dunham@arm.com 11911839SCurtis.Dunham@arm.com#if USE_KVM 12011839SCurtis.Dunham@arm.com if (kvmVM) { 12111839SCurtis.Dunham@arm.com kvmVM->setSystem(this); 12211839SCurtis.Dunham@arm.com } 1238769Sgblack@eecs.umich.edu#endif 1248769Sgblack@eecs.umich.edu 1258769Sgblack@eecs.umich.edu if (FullSystem) { 1268769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1278666SPrakash.Ramrakhyani@arm.com if (!debugSymbolTable) 1288832SAli.Saidi@ARM.com debugSymbolTable = new SymbolTable; 1299814Sandreas.hansson@arm.com } 1309814Sandreas.hansson@arm.com 1319814Sandreas.hansson@arm.com // check if the cache line size is a value known to work 1329814Sandreas.hansson@arm.com if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 1339814Sandreas.hansson@arm.com _cacheLineSize == 64 || _cacheLineSize == 128)) 1348832SAli.Saidi@ARM.com warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 1358832SAli.Saidi@ARM.com 1368832SAli.Saidi@ARM.com // Get the generic system master IDs 1378832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 1388832SAli.Saidi@ARM.com tmp_id = getMasterId(this, "writebacks"); 1398832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 1408832SAli.Saidi@ARM.com tmp_id = getMasterId(this, "functional"); 1418832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 1428832SAli.Saidi@ARM.com tmp_id = getMasterId(this, "interrupt"); 1438885SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1448885SAli.Saidi@ARM.com 1458885SAli.Saidi@ARM.com if (FullSystem) { 1469147Snilay@cs.wisc.edu if (params()->kernel == "") { 1478885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1488885SAli.Saidi@ARM.com "Assuming you know what you're doing\n"); 1498885SAli.Saidi@ARM.com } else { 1508885SAli.Saidi@ARM.com // Get the kernel code 1518885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1528885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1538885SAli.Saidi@ARM.com 1548885SAli.Saidi@ARM.com if (kernel == NULL) 1558885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1568885SAli.Saidi@ARM.com 1578885SAli.Saidi@ARM.com // setup entry points 1588885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1598885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1608885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1618885SAli.Saidi@ARM.com 1628885SAli.Saidi@ARM.com // If load_addr_mask is set to 0x0, then auto-calculate 1638885SAli.Saidi@ARM.com // the smallest mask to cover all kernel addresses so gem5 1648885SAli.Saidi@ARM.com // can relocate the kernel to a new offset. 1658885SAli.Saidi@ARM.com if (loadAddrMask == 0) { 1668885SAli.Saidi@ARM.com Addr shift_amt = findMsbSet(kernelEnd - kernelStart) + 1; 1678885SAli.Saidi@ARM.com loadAddrMask = ((Addr)1 << shift_amt) - 1; 1688885SAli.Saidi@ARM.com } 1698885SAli.Saidi@ARM.com 1708885SAli.Saidi@ARM.com // load symbols 1718885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1728885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1738885SAli.Saidi@ARM.com 1748885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1758885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1768885SAli.Saidi@ARM.com 1778885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 17811838SCurtis.Dunham@arm.com fatal("could not load kernel symbols\n"); 1798885SAli.Saidi@ARM.com 1808885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1819053Sdam.sunwoo@arm.com fatal("could not load kernel local symbols\n"); 1829053Sdam.sunwoo@arm.com 1839053Sdam.sunwoo@arm.com // Loading only needs to happen once and after memory system is 1842SN/A // connected so it will happen in initState() 1852SN/A } 1862SN/A 1872SN/A for (const auto &obj_name : p->kernel_extras) { 1881070SN/A inform("Loading additional kernel object: %s", obj_name); 1891070SN/A ObjectFile *obj = createObjectFile(obj_name); 1908666SPrakash.Ramrakhyani@arm.com fatal_if(!obj, "Failed to additional kernel object '%s'.\n", 1918666SPrakash.Ramrakhyani@arm.com obj_name); 1928666SPrakash.Ramrakhyani@arm.com kernelExtras.push_back(obj); 1932SN/A } 1942SN/A } 1958706Sandreas.hansson@arm.com 1968706Sandreas.hansson@arm.com // increment the number of running systems 1978706Sandreas.hansson@arm.com numSystemsRunning++; 1988706Sandreas.hansson@arm.com 1998706Sandreas.hansson@arm.com // Set back pointers to the system in all memories 2008706Sandreas.hansson@arm.com for (int x = 0; x < params()->memories.size(); x++) 2018706Sandreas.hansson@arm.com params()->memories[x]->system(this); 2028706Sandreas.hansson@arm.com} 2039294Sandreas.hansson@arm.com 2049294Sandreas.hansson@arm.comSystem::~System() 2058703Sandreas.hansson@arm.com{ 2068703Sandreas.hansson@arm.com delete kernelSymtab; 2078922Swilliam.wang@arm.com delete kernel; 2088703Sandreas.hansson@arm.com 2098703Sandreas.hansson@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 2102901Ssaidi@eecs.umich.edu delete workItemStats[j]; 2114762Snate@binkert.org} 2122901Ssaidi@eecs.umich.edu 21310913Sandreas.sandberg@arm.comvoid 2142901Ssaidi@eecs.umich.eduSystem::init() 2152901Ssaidi@eecs.umich.edu{ 2162901Ssaidi@eecs.umich.edu // check that the system port is connected 2173960Sgblack@eecs.umich.edu if (!_systemPort.isConnected()) 2183960Sgblack@eecs.umich.edu panic("System port on %s is not connected.\n", name()); 2194095Sbinkertn@umich.edu} 2204095Sbinkertn@umich.edu 2214095Sbinkertn@umich.eduBaseMasterPort& 2223960Sgblack@eecs.umich.eduSystem::getMasterPort(const std::string &if_name, PortID idx) 2233960Sgblack@eecs.umich.edu{ 2247445Ssteve.reinhardt@amd.com // no need to distinguish at the moment (besides checking) 2257445Ssteve.reinhardt@amd.com return _systemPort; 2267445Ssteve.reinhardt@amd.com} 2277445Ssteve.reinhardt@amd.com 2287445Ssteve.reinhardt@amd.comvoid 2297445Ssteve.reinhardt@amd.comSystem::setMemoryMode(Enums::MemoryMode mode) 2307445Ssteve.reinhardt@amd.com{ 23111005Sandreas.sandberg@arm.com assert(drainState() == DrainState::Drained); 23211005Sandreas.sandberg@arm.com memoryMode = mode; 2332SN/A} 2345712Shsul@eecs.umich.edu 23511005Sandreas.sandberg@arm.combool System::breakpoint() 2365718Shsul@eecs.umich.edu{ 2375718Shsul@eecs.umich.edu if (remoteGDB.size()) 2385718Shsul@eecs.umich.edu return remoteGDB[0]->breakpoint(); 2395718Shsul@eecs.umich.edu return false; 2405718Shsul@eecs.umich.edu} 2415718Shsul@eecs.umich.edu 2425718Shsul@eecs.umich.eduContextID 2435718Shsul@eecs.umich.eduSystem::registerThreadContext(ThreadContext *tc, ContextID assigned) 2445718Shsul@eecs.umich.edu{ 2455718Shsul@eecs.umich.edu int id = assigned; 2465718Shsul@eecs.umich.edu if (id == InvalidContextID) { 2471806SN/A // Find an unused context ID for this thread. 2481806SN/A id = 0; 2492680Sktlim@umich.edu while (id < threadContexts.size() && threadContexts[id]) 2505823Ssaidi@eecs.umich.edu id++; 2511806SN/A } 2522680Sktlim@umich.edu 2535714Shsul@eecs.umich.edu if (threadContexts.size() <= id) 2541070SN/A threadContexts.resize(id + 1); 2559850Sandreas.hansson@arm.com 2565512SMichael.Adler@intel.com fatal_if(threadContexts[id], 2577445Ssteve.reinhardt@amd.com "Cannot have two CPUs with the same id (%d)\n", id); 2584095Sbinkertn@umich.edu 2595512SMichael.Adler@intel.com threadContexts[id] = tc; 2604095Sbinkertn@umich.edu 2617445Ssteve.reinhardt@amd.com#if THE_ISA != NULL_ISA 2624095Sbinkertn@umich.edu int port = getRemoteGDBPort(); 2634095Sbinkertn@umich.edu if (port) { 2641070SN/A RemoteGDB *rgdb = new RemoteGDB(this, tc, port + id); 2654095Sbinkertn@umich.edu rgdb->listen(); 2664095Sbinkertn@umich.edu 2674095Sbinkertn@umich.edu BaseCPU *cpu = tc->getCpuPtr(); 2684095Sbinkertn@umich.edu if (cpu->waitForRemoteGDB()) { 2694095Sbinkertn@umich.edu inform("%s: Waiting for a remote GDB connection on port %d.\n", 2701070SN/A cpu->name(), rgdb->port()); 2719850Sandreas.hansson@arm.com 2721070SN/A rgdb->connect(); 2737914SBrad.Beckmann@amd.com } 2747914SBrad.Beckmann@amd.com if (remoteGDB.size() <= id) { 2751806SN/A remoteGDB.resize(id + 1); 276180SN/A } 27775SN/A 2786029Ssteve.reinhardt@amd.com remoteGDB[id] = rgdb; 2796029Ssteve.reinhardt@amd.com } 2806029Ssteve.reinhardt@amd.com#endif 2816029Ssteve.reinhardt@amd.com 2826029Ssteve.reinhardt@amd.com activeCpus.push_back(false); 2836029Ssteve.reinhardt@amd.com 2846029Ssteve.reinhardt@amd.com return id; 2856029Ssteve.reinhardt@amd.com} 2866029Ssteve.reinhardt@amd.com 2876029Ssteve.reinhardt@amd.comint 2886029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 289180SN/A{ 2907733SAli.Saidi@ARM.com return std::count_if( 2911129SN/A threadContexts.cbegin(), 2928769Sgblack@eecs.umich.edu threadContexts.cend(), 2939172Snilay@cs.wisc.edu [] (ThreadContext* tc) { 2948769Sgblack@eecs.umich.edu return tc->status() != ThreadContext::Halted; 2958799Sgblack@eecs.umich.edu } 2968799Sgblack@eecs.umich.edu ); 2978799Sgblack@eecs.umich.edu} 2988799Sgblack@eecs.umich.edu 2998799Sgblack@eecs.umich.eduvoid 3008885SAli.Saidi@ARM.comSystem::initState() 30110282Sdam.sunwoo@arm.com{ 30210282Sdam.sunwoo@arm.com if (FullSystem) { 30310282Sdam.sunwoo@arm.com for (int i = 0; i < threadContexts.size(); i++) 30410282Sdam.sunwoo@arm.com TheISA::startupCPU(threadContexts[i], i); 30510282Sdam.sunwoo@arm.com // Moved from the constructor to here since it relies on the 30610282Sdam.sunwoo@arm.com // address map being resolved in the interconnect 30710282Sdam.sunwoo@arm.com /** 30810282Sdam.sunwoo@arm.com * Load the kernel code into memory 30910282Sdam.sunwoo@arm.com */ 31010282Sdam.sunwoo@arm.com if (params()->kernel != "") { 31110282Sdam.sunwoo@arm.com if (params()->kernel_addr_check) { 31210282Sdam.sunwoo@arm.com // Validate kernel mapping before loading binary 31310282Sdam.sunwoo@arm.com if (!(isMemAddr((kernelStart & loadAddrMask) + 3149187SKrishnendra.Nathella@arm.com loadAddrOffset) && 3158799Sgblack@eecs.umich.edu isMemAddr((kernelEnd & loadAddrMask) + 31610037SARM gem5 Developers loadAddrOffset))) { 3178706Sandreas.hansson@arm.com fatal("Kernel is mapped to invalid location (not memory). " 3188799Sgblack@eecs.umich.edu "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n", 3198799Sgblack@eecs.umich.edu kernelStart, 3208799Sgblack@eecs.umich.edu kernelEnd, (kernelStart & loadAddrMask) + 3218799Sgblack@eecs.umich.edu loadAddrOffset, 3228799Sgblack@eecs.umich.edu (kernelEnd & loadAddrMask) + loadAddrOffset); 3238706Sandreas.hansson@arm.com } 3241129SN/A } 3251129SN/A // Load program sections into memory 3261129SN/A kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset); 32711005Sandreas.sandberg@arm.com for (const auto &extra_kernel : kernelExtras) { 328180SN/A extra_kernel->loadSections(physProxy, loadAddrMask, 3295713Shsul@eecs.umich.edu loadAddrOffset); 3302680Sktlim@umich.edu } 3315713Shsul@eecs.umich.edu 332180SN/A DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 333180SN/A DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 3345713Shsul@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 3355713Shsul@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 3365713Shsul@eecs.umich.edu } 3372SN/A } 3382SN/A} 33912100SCurtis.Dunham@arm.com 34012100SCurtis.Dunham@arm.comvoid 34112100SCurtis.Dunham@arm.comSystem::replaceThreadContext(ThreadContext *tc, ContextID context_id) 34212100SCurtis.Dunham@arm.com{ 34312100SCurtis.Dunham@arm.com if (context_id >= threadContexts.size()) { 34412100SCurtis.Dunham@arm.com panic("replaceThreadContext: bad id, %d >= %d\n", 34512100SCurtis.Dunham@arm.com context_id, threadContexts.size()); 34612100SCurtis.Dunham@arm.com } 34712100SCurtis.Dunham@arm.com 34812100SCurtis.Dunham@arm.com threadContexts[context_id] = tc; 34912100SCurtis.Dunham@arm.com if (context_id < remoteGDB.size()) 35012100SCurtis.Dunham@arm.com remoteGDB[context_id]->replaceThreadContext(tc); 35112100SCurtis.Dunham@arm.com} 35212100SCurtis.Dunham@arm.com 35312100SCurtis.Dunham@arm.combool 35412100SCurtis.Dunham@arm.comSystem::validKvmEnvironment() const 35512100SCurtis.Dunham@arm.com{ 35612100SCurtis.Dunham@arm.com#if USE_KVM 3572378SN/A if (threadContexts.empty()) 3588601Ssteve.reinhardt@amd.com return false; 3592378SN/A 36010318Sandreas.hansson@arm.com for (auto tc : threadContexts) { 3618601Ssteve.reinhardt@amd.com if (dynamic_cast<BaseKvmCPU*>(tc->getCpuPtr()) == nullptr) { 36210553Salexandru.dutu@amd.com return false; 36310553Salexandru.dutu@amd.com } 36410553Salexandru.dutu@amd.com } 36510553Salexandru.dutu@amd.com return true; 36610553Salexandru.dutu@amd.com#else 36710553Salexandru.dutu@amd.com return false; 36810553Salexandru.dutu@amd.com#endif 36910553Salexandru.dutu@amd.com} 37010553Salexandru.dutu@amd.com 37110553Salexandru.dutu@amd.comAddr 37210318Sandreas.hansson@arm.comSystem::allocPhysPages(int npages) 3733162Ssaidi@eecs.umich.edu{ 3742378SN/A Addr return_addr = pagePtr << PageShift; 3752378SN/A pagePtr += npages; 3765795Ssaidi@eecs.umich.edu 3775795Ssaidi@eecs.umich.edu Addr next_return_addr = pagePtr << PageShift; 3788931Sandreas.hansson@arm.com 3795795Ssaidi@eecs.umich.edu AddrRange m5opRange(0xffff0000, 0xffffffff); 3808931Sandreas.hansson@arm.com if (m5opRange.contains(next_return_addr)) { 3815795Ssaidi@eecs.umich.edu warn("Reached m5ops MMIO region\n"); 3825795Ssaidi@eecs.umich.edu return_addr = 0xffffffff; 3835795Ssaidi@eecs.umich.edu pagePtr = 0xffffffff >> PageShift; 3848931Sandreas.hansson@arm.com } 3855795Ssaidi@eecs.umich.edu 38610318Sandreas.hansson@arm.com if ((pagePtr << PageShift) > physmem.totalSize()) 3875795Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3885795Ssaidi@eecs.umich.edu return return_addr; 3898460SAli.Saidi@ARM.com} 3908931Sandreas.hansson@arm.com 3918460SAli.Saidi@ARM.comAddr 3928931Sandreas.hansson@arm.comSystem::memSize() const 3938460SAli.Saidi@ARM.com{ 3948460SAli.Saidi@ARM.com return physmem.totalSize(); 3951070SN/A} 3969342SAndreas.Sandberg@arm.com 3977897Shestness@cs.utexas.eduAddr 3987897Shestness@cs.utexas.eduSystem::freeMemSize() const 3997897Shestness@cs.utexas.edu{ 4007897Shestness@cs.utexas.edu return physmem.totalSize() - (pagePtr << PageShift); 4017897Shestness@cs.utexas.edu} 40210905Sandreas.sandberg@arm.com 4031070SN/Abool 4048769Sgblack@eecs.umich.eduSystem::isMemAddr(Addr addr) const 40510905Sandreas.sandberg@arm.com{ 4067770SAli.Saidi@ARM.com return physmem.isMemAddr(addr); 40710905Sandreas.sandberg@arm.com} 4089293Sandreas.hansson@arm.com 4099293Sandreas.hansson@arm.comvoid 41010905Sandreas.sandberg@arm.comSystem::drainResume() 4111070SN/A{ 4121070SN/A totalNumInsts = 0; 4131070SN/A} 4141070SN/A 41510905Sandreas.sandberg@arm.comvoid 4161070SN/ASystem::serialize(CheckpointOut &cp) const 4178769Sgblack@eecs.umich.edu{ 41810905Sandreas.sandberg@arm.com if (FullSystem) 4197770SAli.Saidi@ARM.com kernelSymtab->serialize("kernel_symtab", cp); 42010905Sandreas.sandberg@arm.com SERIALIZE_SCALAR(pagePtr); 4219293Sandreas.hansson@arm.com serializeSymtab(cp); 4229293Sandreas.hansson@arm.com 42310905Sandreas.sandberg@arm.com // also serialize the memories in the system 4241070SN/A physmem.serializeSection(cp, "physmem"); 4252SN/A} 4262SN/A 4278666SPrakash.Ramrakhyani@arm.com 4288666SPrakash.Ramrakhyani@arm.comvoid 42911522Sstephan.diestelhorst@arm.comSystem::unserialize(CheckpointIn &cp) 43011522Sstephan.diestelhorst@arm.com{ 4318666SPrakash.Ramrakhyani@arm.com if (FullSystem) 4328666SPrakash.Ramrakhyani@arm.com kernelSymtab->unserialize("kernel_symtab", cp); 4338666SPrakash.Ramrakhyani@arm.com UNSERIALIZE_SCALAR(pagePtr); 4348666SPrakash.Ramrakhyani@arm.com unserializeSymtab(cp); 4358666SPrakash.Ramrakhyani@arm.com 4368666SPrakash.Ramrakhyani@arm.com // also unserialize the memories in the system 4378666SPrakash.Ramrakhyani@arm.com physmem.unserializeSection(cp, "physmem"); 4388666SPrakash.Ramrakhyani@arm.com} 4398666SPrakash.Ramrakhyani@arm.com 4408666SPrakash.Ramrakhyani@arm.comvoid 4418666SPrakash.Ramrakhyani@arm.comSystem::regStats() 4428666SPrakash.Ramrakhyani@arm.com{ 4438666SPrakash.Ramrakhyani@arm.com MemObject::regStats(); 4448666SPrakash.Ramrakhyani@arm.com 4458666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 4468666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 4478666SPrakash.Ramrakhyani@arm.com stringstream namestr; 4488666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 4498666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 4508666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 4518666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 4528666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 4538666SPrakash.Ramrakhyani@arm.com } 4548666SPrakash.Ramrakhyani@arm.com} 4558666SPrakash.Ramrakhyani@arm.com 4568666SPrakash.Ramrakhyani@arm.comvoid 4578666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 4588666SPrakash.Ramrakhyani@arm.com{ 4598666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4602SN/A if (!lastWorkItemStarted.count(p)) 4612SN/A return; 46210375Sandreas.hansson@arm.com 46310375Sandreas.hansson@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 4642SN/A DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 4652SN/A 4662SN/A if (workid >= numWorkIds) 4672SN/A fatal("Got workid greater than specified in system configuration\n"); 4682SN/A 4692SN/A workItemStats[workid]->sample(samp); 47010375Sandreas.hansson@arm.com lastWorkItemStarted.erase(p); 47110375Sandreas.hansson@arm.com} 4722SN/A 4732SN/Avoid 4742SN/ASystem::printSystems() 4752SN/A{ 4762SN/A ios::fmtflags flags(cerr.flags()); 4772SN/A 4782SN/A vector<System *>::iterator i = systemList.begin(); 4792SN/A vector<System *>::iterator end = systemList.end(); 4808832SAli.Saidi@ARM.com for (; i != end; ++i) { 4818832SAli.Saidi@ARM.com System *sys = *i; 4828832SAli.Saidi@ARM.com cerr << "System " << sys->name() << ": " << hex << sys << endl; 4838832SAli.Saidi@ARM.com } 4849142Ssteve.reinhardt@amd.com 4858832SAli.Saidi@ARM.com cerr.flags(flags); 4868832SAli.Saidi@ARM.com} 4878832SAli.Saidi@ARM.com 4888832SAli.Saidi@ARM.comvoid 4898832SAli.Saidi@ARM.comprintSystems() 4908832SAli.Saidi@ARM.com{ 4918832SAli.Saidi@ARM.com System::printSystems(); 4928832SAli.Saidi@ARM.com} 4938832SAli.Saidi@ARM.com 4948986SAli.Saidi@ARM.comMasterID 4958986SAli.Saidi@ARM.comSystem::getGlobalMasterId(std::string master_name) 4968986SAli.Saidi@ARM.com{ 4978832SAli.Saidi@ARM.com return _getMasterId(nullptr, master_name); 49810367SAndrew.Bardsley@arm.com} 49910367SAndrew.Bardsley@arm.com 50010367SAndrew.Bardsley@arm.comMasterID 50110367SAndrew.Bardsley@arm.comSystem::getMasterId(const SimObject* master, std::string submaster) 5028832SAli.Saidi@ARM.com{ 5038832SAli.Saidi@ARM.com auto master_name = leafMasterName(master, submaster); 5048832SAli.Saidi@ARM.com return _getMasterId(master, master_name); 5058832SAli.Saidi@ARM.com} 5068832SAli.Saidi@ARM.com 5078832SAli.Saidi@ARM.comMasterID 5088832SAli.Saidi@ARM.comSystem::_getMasterId(const SimObject* master, std::string master_name) 5098832SAli.Saidi@ARM.com{ 5108832SAli.Saidi@ARM.com if (startswith(master_name, name())) 5118832SAli.Saidi@ARM.com master_name = master_name.erase(0, name().size() + 1); 5128832SAli.Saidi@ARM.com 5138832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 5148832SAli.Saidi@ARM.com for (int i = 0; i < masters.size(); i++) { 5158832SAli.Saidi@ARM.com if (masters[i].masterName == master_name) { 5168832SAli.Saidi@ARM.com return i; 5174762Snate@binkert.org } 5184762Snate@binkert.org } 5192424SN/A 5205530Snate@binkert.org // Verify that the statistics haven't been enabled yet 5212424SN/A // Otherwise objects will have sized their stat buckets and 522 // they will be too small 523 524 if (Stats::enabled()) { 525 fatal("Can't request a masterId after regStats(). " 526 "You must do so in init().\n"); 527 } 528 529 // Generate a new MasterID incrementally 530 MasterID master_id = masters.size(); 531 532 // Append the new Master metadata to the group of system Masters. 533 masters.emplace_back(master, master_name, master_id); 534 535 return masters.back().masterId; 536} 537 538std::string 539System::leafMasterName(const SimObject* master, const std::string& submaster) 540{ 541 if (submaster.empty()) { 542 return master->name(); 543 } else { 544 // Get the full master name by appending the submaster name to 545 // the root SimObject master name 546 return master->name() + "." + submaster; 547 } 548} 549 550std::string 551System::getMasterName(MasterID master_id) 552{ 553 if (master_id >= masters.size()) 554 fatal("Invalid master_id passed to getMasterName()\n"); 555 556 const auto& master_info = masters[master_id]; 557 return master_info.masterName; 558} 559 560System * 561SystemParams::create() 562{ 563 return new System(this); 564} 565