system.cc revision 10700
12689Sktlim@umich.edu/* 210282Sdam.sunwoo@arm.com * Copyright (c) 2011-2014 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 483960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 494194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 501070SN/A#include "base/loader/object_file.hh" 511070SN/A#include "base/loader/symtab.hh" 529142Ssteve.reinhardt@amd.com#include "base/str.hh" 532521SN/A#include "base/trace.hh" 548229Snate@binkert.org#include "cpu/thread_context.hh" 558232Snate@binkert.org#include "debug/Loader.hh" 568666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 579293Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 582522SN/A#include "mem/physical.hh" 598769Sgblack@eecs.umich.edu#include "params/System.hh" 602037SN/A#include "sim/byteswap.hh" 618229Snate@binkert.org#include "sim/debug.hh" 628769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 6356SN/A#include "sim/system.hh" 646658Snate@binkert.org 6510494Sandreas.hansson@arm.com/** 6610494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 6710494Sandreas.hansson@arm.com * actually have a definition. 6810494Sandreas.hansson@arm.com */ 6910494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7010494Sandreas.hansson@arm.com#include "kern/kernel_stats.hh" 7110494Sandreas.hansson@arm.com#endif 7210494Sandreas.hansson@arm.com 732SN/Ausing namespace std; 742107SN/Ausing namespace TheISA; 752SN/A 762SN/Avector<System *> System::systemList; 772SN/A 782SN/Aint System::numSystemsRunning = 0; 792SN/A 801070SN/ASystem::System(Params *p) 818703Sandreas.hansson@arm.com : MemObject(p), _systemPort("system_port", this), 828703Sandreas.hansson@arm.com _numContexts(0), 838826Snilay@cs.wisc.edu pagePtr(0), 842521SN/A init_param(p->init_param), 859814Sandreas.hansson@arm.com physProxy(_systemPort, p->cache_line_size), 8610360Sandreas.hansson@arm.com kernelSymtab(nullptr), 8710360Sandreas.hansson@arm.com kernel(nullptr), 887580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 8910037SARM gem5 Developers loadAddrOffset(p->load_offset), 907770SAli.Saidi@ARM.com nextPID(0), 9110700Sandreas.hansson@arm.com physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve), 927914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 939814Sandreas.hansson@arm.com _cacheLineSize(p->cache_line_size), 947914SBrad.Beckmann@amd.com workItemsBegin(0), 957914SBrad.Beckmann@amd.com workItemsEnd(0), 968666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 977914SBrad.Beckmann@amd.com _params(p), 988666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 997897Shestness@cs.utexas.edu instEventQueue("system instruction-based event queue") 1002SN/A{ 1011070SN/A // add self to global system list 1021070SN/A systemList.push_back(this); 1031070SN/A 1048769Sgblack@eecs.umich.edu if (FullSystem) { 1058769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1068769Sgblack@eecs.umich.edu if (!debugSymbolTable) 1078769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 1088666SPrakash.Ramrakhyani@arm.com } 1098832SAli.Saidi@ARM.com 1109814Sandreas.hansson@arm.com // check if the cache line size is a value known to work 1119814Sandreas.hansson@arm.com if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 1129814Sandreas.hansson@arm.com _cacheLineSize == 64 || _cacheLineSize == 128)) 1139814Sandreas.hansson@arm.com warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 1149814Sandreas.hansson@arm.com 1158832SAli.Saidi@ARM.com // Get the generic system master IDs 1168832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 1178832SAli.Saidi@ARM.com tmp_id = getMasterId("writebacks"); 1188832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 1198832SAli.Saidi@ARM.com tmp_id = getMasterId("functional"); 1208832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 1218832SAli.Saidi@ARM.com tmp_id = getMasterId("interrupt"); 1228832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1238832SAli.Saidi@ARM.com 1248885SAli.Saidi@ARM.com if (FullSystem) { 1258885SAli.Saidi@ARM.com if (params()->kernel == "") { 1268885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1279147Snilay@cs.wisc.edu "Assuming you know what you're doing\n"); 1288885SAli.Saidi@ARM.com } else { 1298885SAli.Saidi@ARM.com // Get the kernel code 1308885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1318885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1328885SAli.Saidi@ARM.com 1338885SAli.Saidi@ARM.com if (kernel == NULL) 1348885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1358885SAli.Saidi@ARM.com 1368885SAli.Saidi@ARM.com // setup entry points 1378885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1388885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1398885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1408885SAli.Saidi@ARM.com 1418885SAli.Saidi@ARM.com // load symbols 1428885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1438885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1448885SAli.Saidi@ARM.com 1458885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1468885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1478885SAli.Saidi@ARM.com 1488885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 1498885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1508885SAli.Saidi@ARM.com 1518885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1528885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1538885SAli.Saidi@ARM.com 1548885SAli.Saidi@ARM.com // Loading only needs to happen once and after memory system is 1558885SAli.Saidi@ARM.com // connected so it will happen in initState() 1568885SAli.Saidi@ARM.com } 1578885SAli.Saidi@ARM.com } 1588885SAli.Saidi@ARM.com 1598885SAli.Saidi@ARM.com // increment the number of running systms 1608885SAli.Saidi@ARM.com numSystemsRunning++; 1618885SAli.Saidi@ARM.com 1629053Sdam.sunwoo@arm.com // Set back pointers to the system in all memories 1639053Sdam.sunwoo@arm.com for (int x = 0; x < params()->memories.size(); x++) 1649053Sdam.sunwoo@arm.com params()->memories[x]->system(this); 1652SN/A} 1662SN/A 1672SN/ASystem::~System() 1682SN/A{ 1691070SN/A delete kernelSymtab; 1701070SN/A delete kernel; 1718666SPrakash.Ramrakhyani@arm.com 1728666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 1738666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 1742SN/A} 1752SN/A 1768706Sandreas.hansson@arm.comvoid 1778706Sandreas.hansson@arm.comSystem::init() 1788706Sandreas.hansson@arm.com{ 1798706Sandreas.hansson@arm.com // check that the system port is connected 1808706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 1818706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 1828706Sandreas.hansson@arm.com} 1838706Sandreas.hansson@arm.com 1849294Sandreas.hansson@arm.comBaseMasterPort& 1859294Sandreas.hansson@arm.comSystem::getMasterPort(const std::string &if_name, PortID idx) 1868703Sandreas.hansson@arm.com{ 1878703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 1888922Swilliam.wang@arm.com return _systemPort; 1898703Sandreas.hansson@arm.com} 1908703Sandreas.hansson@arm.com 1912901Ssaidi@eecs.umich.eduvoid 1924762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 1932901Ssaidi@eecs.umich.edu{ 1949342SAndreas.Sandberg@arm.com assert(getDrainState() == Drainable::Drained); 1952901Ssaidi@eecs.umich.edu memoryMode = mode; 1962901Ssaidi@eecs.umich.edu} 1972901Ssaidi@eecs.umich.edu 1983960Sgblack@eecs.umich.edubool System::breakpoint() 1993960Sgblack@eecs.umich.edu{ 2004095Sbinkertn@umich.edu if (remoteGDB.size()) 2014095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 2024095Sbinkertn@umich.edu return false; 2033960Sgblack@eecs.umich.edu} 2043960Sgblack@eecs.umich.edu 2057445Ssteve.reinhardt@amd.com/** 2067445Ssteve.reinhardt@amd.com * Setting rgdb_wait to a positive integer waits for a remote debugger to 2077445Ssteve.reinhardt@amd.com * connect to that context ID before continuing. This should really 2087445Ssteve.reinhardt@amd.com be a parameter on the CPU object or something... 2097445Ssteve.reinhardt@amd.com */ 2107445Ssteve.reinhardt@amd.comint rgdb_wait = -1; 2117445Ssteve.reinhardt@amd.com 212180SN/Aint 2135718Shsul@eecs.umich.eduSystem::registerThreadContext(ThreadContext *tc, int assigned) 2142SN/A{ 2155712Shsul@eecs.umich.edu int id; 2165718Shsul@eecs.umich.edu if (assigned == -1) { 2175718Shsul@eecs.umich.edu for (id = 0; id < threadContexts.size(); id++) { 2185718Shsul@eecs.umich.edu if (!threadContexts[id]) 2195718Shsul@eecs.umich.edu break; 2205718Shsul@eecs.umich.edu } 2215718Shsul@eecs.umich.edu 2225718Shsul@eecs.umich.edu if (threadContexts.size() <= id) 2235718Shsul@eecs.umich.edu threadContexts.resize(id + 1); 2245718Shsul@eecs.umich.edu } else { 2255718Shsul@eecs.umich.edu if (threadContexts.size() <= assigned) 2265718Shsul@eecs.umich.edu threadContexts.resize(assigned + 1); 2275718Shsul@eecs.umich.edu id = assigned; 2281806SN/A } 2291806SN/A 2302680Sktlim@umich.edu if (threadContexts[id]) 2315823Ssaidi@eecs.umich.edu fatal("Cannot have two CPUs with the same id (%d)\n", id); 2321806SN/A 2332680Sktlim@umich.edu threadContexts[id] = tc; 2345714Shsul@eecs.umich.edu _numContexts++; 2351070SN/A 2369850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 2375512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 2387445Ssteve.reinhardt@amd.com if (port) { 2394095Sbinkertn@umich.edu RemoteGDB *rgdb = new RemoteGDB(this, tc); 2405512SMichael.Adler@intel.com GDBListener *gdbl = new GDBListener(rgdb, port + id); 2414095Sbinkertn@umich.edu gdbl->listen(); 2427445Ssteve.reinhardt@amd.com 2434095Sbinkertn@umich.edu if (rgdb_wait != -1 && rgdb_wait == id) 2444095Sbinkertn@umich.edu gdbl->accept(); 2451070SN/A 2464095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2474095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2484095Sbinkertn@umich.edu } 2494095Sbinkertn@umich.edu 2504095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2511070SN/A } 2529850Sandreas.hansson@arm.com#endif 2531070SN/A 2547914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2557914SBrad.Beckmann@amd.com 2561806SN/A return id; 257180SN/A} 25875SN/A 2596029Ssteve.reinhardt@amd.comint 2606029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2616029Ssteve.reinhardt@amd.com{ 2626029Ssteve.reinhardt@amd.com int running = 0; 2636029Ssteve.reinhardt@amd.com for (int i = 0; i < _numContexts; ++i) { 2646029Ssteve.reinhardt@amd.com if (threadContexts[i]->status() != ThreadContext::Halted) 2656029Ssteve.reinhardt@amd.com ++running; 2666029Ssteve.reinhardt@amd.com } 2676029Ssteve.reinhardt@amd.com return running; 2686029Ssteve.reinhardt@amd.com} 2696029Ssteve.reinhardt@amd.com 270180SN/Avoid 2717733SAli.Saidi@ARM.comSystem::initState() 2721129SN/A{ 2738769Sgblack@eecs.umich.edu if (FullSystem) { 2749172Snilay@cs.wisc.edu for (int i = 0; i < threadContexts.size(); i++) 2758769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2768799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 2778799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 2788799Sgblack@eecs.umich.edu /** 2798799Sgblack@eecs.umich.edu * Load the kernel code into memory 2808799Sgblack@eecs.umich.edu */ 2818885SAli.Saidi@ARM.com if (params()->kernel != "") { 28210282Sdam.sunwoo@arm.com if (params()->kernel_addr_check) { 28310282Sdam.sunwoo@arm.com // Validate kernel mapping before loading binary 28410282Sdam.sunwoo@arm.com if (!(isMemAddr((kernelStart & loadAddrMask) + 28510282Sdam.sunwoo@arm.com loadAddrOffset) && 28610282Sdam.sunwoo@arm.com isMemAddr((kernelEnd & loadAddrMask) + 28710282Sdam.sunwoo@arm.com loadAddrOffset))) { 28810282Sdam.sunwoo@arm.com fatal("Kernel is mapped to invalid location (not memory). " 28910282Sdam.sunwoo@arm.com "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n", 29010282Sdam.sunwoo@arm.com kernelStart, 29110282Sdam.sunwoo@arm.com kernelEnd, (kernelStart & loadAddrMask) + 29210282Sdam.sunwoo@arm.com loadAddrOffset, 29310282Sdam.sunwoo@arm.com (kernelEnd & loadAddrMask) + loadAddrOffset); 29410282Sdam.sunwoo@arm.com } 2959187SKrishnendra.Nathella@arm.com } 2968799Sgblack@eecs.umich.edu // Load program sections into memory 29710037SARM gem5 Developers kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset); 2988706Sandreas.hansson@arm.com 2998799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 3008799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 3018799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 3028799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 3038799Sgblack@eecs.umich.edu } 3048706Sandreas.hansson@arm.com } 3058706Sandreas.hansson@arm.com 3068706Sandreas.hansson@arm.com activeCpus.clear(); 3071129SN/A} 3081129SN/A 3091129SN/Avoid 3105713Shsul@eecs.umich.eduSystem::replaceThreadContext(ThreadContext *tc, int context_id) 311180SN/A{ 3125713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 3132680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 3145713Shsul@eecs.umich.edu context_id, threadContexts.size()); 315180SN/A } 316180SN/A 3175713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 3185713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 3195713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 3202SN/A} 3212SN/A 3222378SN/AAddr 3238601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 3242378SN/A{ 32510318Sandreas.hansson@arm.com Addr return_addr = pagePtr << PageShift; 3268601Ssteve.reinhardt@amd.com pagePtr += npages; 32710553Salexandru.dutu@amd.com 32810553Salexandru.dutu@amd.com Addr next_return_addr = pagePtr << PageShift; 32910553Salexandru.dutu@amd.com 33010553Salexandru.dutu@amd.com AddrRange m5opRange(0xffff0000, 0xffffffff); 33110553Salexandru.dutu@amd.com if (m5opRange.contains(next_return_addr)) { 33210553Salexandru.dutu@amd.com warn("Reached m5ops MMIO region\n"); 33310553Salexandru.dutu@amd.com return_addr = 0xffffffff; 33410553Salexandru.dutu@amd.com pagePtr = 0xffffffff >> PageShift; 33510553Salexandru.dutu@amd.com } 33610553Salexandru.dutu@amd.com 33710318Sandreas.hansson@arm.com if ((pagePtr << PageShift) > physmem.totalSize()) 3383162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3392378SN/A return return_addr; 3402378SN/A} 3415795Ssaidi@eecs.umich.edu 3425795Ssaidi@eecs.umich.eduAddr 3438931Sandreas.hansson@arm.comSystem::memSize() const 3445795Ssaidi@eecs.umich.edu{ 3458931Sandreas.hansson@arm.com return physmem.totalSize(); 3465795Ssaidi@eecs.umich.edu} 3475795Ssaidi@eecs.umich.edu 3485795Ssaidi@eecs.umich.eduAddr 3498931Sandreas.hansson@arm.comSystem::freeMemSize() const 3505795Ssaidi@eecs.umich.edu{ 35110318Sandreas.hansson@arm.com return physmem.totalSize() - (pagePtr << PageShift); 3525795Ssaidi@eecs.umich.edu} 3535795Ssaidi@eecs.umich.edu 3548460SAli.Saidi@ARM.combool 3558931Sandreas.hansson@arm.comSystem::isMemAddr(Addr addr) const 3568460SAli.Saidi@ARM.com{ 3578931Sandreas.hansson@arm.com return physmem.isMemAddr(addr); 3588460SAli.Saidi@ARM.com} 3598460SAli.Saidi@ARM.com 3609342SAndreas.Sandberg@arm.comunsigned int 3619342SAndreas.Sandberg@arm.comSystem::drain(DrainManager *dm) 3629342SAndreas.Sandberg@arm.com{ 3639342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 3649342SAndreas.Sandberg@arm.com return 0; 3659342SAndreas.Sandberg@arm.com} 3669342SAndreas.Sandberg@arm.com 3671070SN/Avoid 3689342SAndreas.Sandberg@arm.comSystem::drainResume() 3697897Shestness@cs.utexas.edu{ 3709342SAndreas.Sandberg@arm.com Drainable::drainResume(); 3717897Shestness@cs.utexas.edu totalNumInsts = 0; 3727897Shestness@cs.utexas.edu} 3737897Shestness@cs.utexas.edu 3747897Shestness@cs.utexas.eduvoid 3751070SN/ASystem::serialize(ostream &os) 3761070SN/A{ 3778769Sgblack@eecs.umich.edu if (FullSystem) 3788769Sgblack@eecs.umich.edu kernelSymtab->serialize("kernel_symtab", os); 3797770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 3807770SAli.Saidi@ARM.com SERIALIZE_SCALAR(nextPID); 3819292Sandreas.hansson@arm.com serializeSymtab(os); 3829293Sandreas.hansson@arm.com 3839293Sandreas.hansson@arm.com // also serialize the memories in the system 3849293Sandreas.hansson@arm.com nameOut(os, csprintf("%s.physmem", name())); 3859293Sandreas.hansson@arm.com physmem.serialize(os); 3861070SN/A} 3871070SN/A 3881070SN/A 3891070SN/Avoid 3901070SN/ASystem::unserialize(Checkpoint *cp, const string §ion) 3911070SN/A{ 3928769Sgblack@eecs.umich.edu if (FullSystem) 3938769Sgblack@eecs.umich.edu kernelSymtab->unserialize("kernel_symtab", cp, section); 3947770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 3957770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(nextPID); 3969292Sandreas.hansson@arm.com unserializeSymtab(cp, section); 3979293Sandreas.hansson@arm.com 3989293Sandreas.hansson@arm.com // also unserialize the memories in the system 3999293Sandreas.hansson@arm.com physmem.unserialize(cp, csprintf("%s.physmem", name())); 4001070SN/A} 4012SN/A 4022SN/Avoid 4038666SPrakash.Ramrakhyani@arm.comSystem::regStats() 4048666SPrakash.Ramrakhyani@arm.com{ 4058666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 4068666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 4078666SPrakash.Ramrakhyani@arm.com stringstream namestr; 4088666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 4098666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 4108666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 4118666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 4128666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 4138666SPrakash.Ramrakhyani@arm.com } 4148666SPrakash.Ramrakhyani@arm.com} 4158666SPrakash.Ramrakhyani@arm.com 4168666SPrakash.Ramrakhyani@arm.comvoid 4178666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 4188666SPrakash.Ramrakhyani@arm.com{ 4198666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4208666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 4218666SPrakash.Ramrakhyani@arm.com return; 4228666SPrakash.Ramrakhyani@arm.com 4238666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 4248666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 4258666SPrakash.Ramrakhyani@arm.com 4268666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 4278666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 4288666SPrakash.Ramrakhyani@arm.com 4298666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 4308666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 4318666SPrakash.Ramrakhyani@arm.com} 4328666SPrakash.Ramrakhyani@arm.com 4338666SPrakash.Ramrakhyani@arm.comvoid 4342SN/ASystem::printSystems() 4352SN/A{ 43610375Sandreas.hansson@arm.com ios::fmtflags flags(cerr.flags()); 43710375Sandreas.hansson@arm.com 4382SN/A vector<System *>::iterator i = systemList.begin(); 4392SN/A vector<System *>::iterator end = systemList.end(); 4402SN/A for (; i != end; ++i) { 4412SN/A System *sys = *i; 4422SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 4432SN/A } 44410375Sandreas.hansson@arm.com 44510375Sandreas.hansson@arm.com cerr.flags(flags); 4462SN/A} 4472SN/A 4482SN/Avoid 4492SN/AprintSystems() 4502SN/A{ 4512SN/A System::printSystems(); 4522SN/A} 4532SN/A 4548832SAli.Saidi@ARM.comMasterID 4558832SAli.Saidi@ARM.comSystem::getMasterId(std::string master_name) 4568832SAli.Saidi@ARM.com{ 4578832SAli.Saidi@ARM.com // strip off system name if the string starts with it 4589142Ssteve.reinhardt@amd.com if (startswith(master_name, name())) 4598832SAli.Saidi@ARM.com master_name = master_name.erase(0, name().size() + 1); 4608832SAli.Saidi@ARM.com 4618832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 4628832SAli.Saidi@ARM.com for (int i = 0; i < masterIds.size(); i++) { 4638832SAli.Saidi@ARM.com if (masterIds[i] == master_name) { 4648832SAli.Saidi@ARM.com return i; 4658832SAli.Saidi@ARM.com } 4668832SAli.Saidi@ARM.com } 4678832SAli.Saidi@ARM.com 4688986SAli.Saidi@ARM.com // Verify that the statistics haven't been enabled yet 4698986SAli.Saidi@ARM.com // Otherwise objects will have sized their stat buckets and 4708986SAli.Saidi@ARM.com // they will be too small 4718832SAli.Saidi@ARM.com 47210367SAndrew.Bardsley@arm.com if (Stats::enabled()) { 47310367SAndrew.Bardsley@arm.com fatal("Can't request a masterId after regStats(). " 47410367SAndrew.Bardsley@arm.com "You must do so in init().\n"); 47510367SAndrew.Bardsley@arm.com } 4768832SAli.Saidi@ARM.com 4778832SAli.Saidi@ARM.com masterIds.push_back(master_name); 4788832SAli.Saidi@ARM.com 4798832SAli.Saidi@ARM.com return masterIds.size() - 1; 4808832SAli.Saidi@ARM.com} 4818832SAli.Saidi@ARM.com 4828832SAli.Saidi@ARM.comstd::string 4838832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 4848832SAli.Saidi@ARM.com{ 4858832SAli.Saidi@ARM.com if (master_id >= masterIds.size()) 4868832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 4878832SAli.Saidi@ARM.com 4888832SAli.Saidi@ARM.com return masterIds[master_id]; 4898832SAli.Saidi@ARM.com} 4908832SAli.Saidi@ARM.com 4914762Snate@binkert.orgSystem * 4924762Snate@binkert.orgSystemParams::create() 4932424SN/A{ 4945530Snate@binkert.org return new System(this); 4952424SN/A} 496