system.cc revision 10360
12689Sktlim@umich.edu/* 210282Sdam.sunwoo@arm.com * Copyright (c) 2011-2014 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 482521SN/A#include "arch/isa_traits.hh" 493960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 504194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 511070SN/A#include "base/loader/object_file.hh" 521070SN/A#include "base/loader/symtab.hh" 539142Ssteve.reinhardt@amd.com#include "base/str.hh" 542521SN/A#include "base/trace.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568229Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Loader.hh" 588666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 598769Sgblack@eecs.umich.edu#include "kern/kernel_stats.hh" 609293Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 612522SN/A#include "mem/physical.hh" 628769Sgblack@eecs.umich.edu#include "params/System.hh" 632037SN/A#include "sim/byteswap.hh" 648229Snate@binkert.org#include "sim/debug.hh" 658769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 6656SN/A#include "sim/system.hh" 676658Snate@binkert.org 682SN/Ausing namespace std; 692107SN/Ausing namespace TheISA; 702SN/A 712SN/Avector<System *> System::systemList; 722SN/A 732SN/Aint System::numSystemsRunning = 0; 742SN/A 751070SN/ASystem::System(Params *p) 768703Sandreas.hansson@arm.com : MemObject(p), _systemPort("system_port", this), 778703Sandreas.hansson@arm.com _numContexts(0), 788826Snilay@cs.wisc.edu pagePtr(0), 792521SN/A init_param(p->init_param), 809814Sandreas.hansson@arm.com physProxy(_systemPort, p->cache_line_size), 8110360Sandreas.hansson@arm.com kernelSymtab(nullptr), 8210360Sandreas.hansson@arm.com kernel(nullptr), 837580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 8410037SARM gem5 Developers loadAddrOffset(p->load_offset), 857770SAli.Saidi@ARM.com nextPID(0), 869293Sandreas.hansson@arm.com physmem(name() + ".physmem", p->memories), 877914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 889814Sandreas.hansson@arm.com _cacheLineSize(p->cache_line_size), 897914SBrad.Beckmann@amd.com workItemsBegin(0), 907914SBrad.Beckmann@amd.com workItemsEnd(0), 918666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 927914SBrad.Beckmann@amd.com _params(p), 938666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 947897Shestness@cs.utexas.edu instEventQueue("system instruction-based event queue") 952SN/A{ 961070SN/A // add self to global system list 971070SN/A systemList.push_back(this); 981070SN/A 998769Sgblack@eecs.umich.edu if (FullSystem) { 1008769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1018769Sgblack@eecs.umich.edu if (!debugSymbolTable) 1028769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 1038666SPrakash.Ramrakhyani@arm.com } 1048832SAli.Saidi@ARM.com 1059814Sandreas.hansson@arm.com // check if the cache line size is a value known to work 1069814Sandreas.hansson@arm.com if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 1079814Sandreas.hansson@arm.com _cacheLineSize == 64 || _cacheLineSize == 128)) 1089814Sandreas.hansson@arm.com warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 1099814Sandreas.hansson@arm.com 1108832SAli.Saidi@ARM.com // Get the generic system master IDs 1118832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 1128832SAli.Saidi@ARM.com tmp_id = getMasterId("writebacks"); 1138832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 1148832SAli.Saidi@ARM.com tmp_id = getMasterId("functional"); 1158832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 1168832SAli.Saidi@ARM.com tmp_id = getMasterId("interrupt"); 1178832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1188832SAli.Saidi@ARM.com 1198885SAli.Saidi@ARM.com if (FullSystem) { 1208885SAli.Saidi@ARM.com if (params()->kernel == "") { 1218885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1229147Snilay@cs.wisc.edu "Assuming you know what you're doing\n"); 1238885SAli.Saidi@ARM.com } else { 1248885SAli.Saidi@ARM.com // Get the kernel code 1258885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1268885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1278885SAli.Saidi@ARM.com 1288885SAli.Saidi@ARM.com if (kernel == NULL) 1298885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1308885SAli.Saidi@ARM.com 1318885SAli.Saidi@ARM.com // setup entry points 1328885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1338885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1348885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1358885SAli.Saidi@ARM.com 1368885SAli.Saidi@ARM.com // load symbols 1378885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1388885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1398885SAli.Saidi@ARM.com 1408885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1418885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1428885SAli.Saidi@ARM.com 1438885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 1448885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1458885SAli.Saidi@ARM.com 1468885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1478885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1488885SAli.Saidi@ARM.com 1498885SAli.Saidi@ARM.com // Loading only needs to happen once and after memory system is 1508885SAli.Saidi@ARM.com // connected so it will happen in initState() 1518885SAli.Saidi@ARM.com } 1528885SAli.Saidi@ARM.com } 1538885SAli.Saidi@ARM.com 1548885SAli.Saidi@ARM.com // increment the number of running systms 1558885SAli.Saidi@ARM.com numSystemsRunning++; 1568885SAli.Saidi@ARM.com 1579053Sdam.sunwoo@arm.com // Set back pointers to the system in all memories 1589053Sdam.sunwoo@arm.com for (int x = 0; x < params()->memories.size(); x++) 1599053Sdam.sunwoo@arm.com params()->memories[x]->system(this); 1602SN/A} 1612SN/A 1622SN/ASystem::~System() 1632SN/A{ 1641070SN/A delete kernelSymtab; 1651070SN/A delete kernel; 1668666SPrakash.Ramrakhyani@arm.com 1678666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 1688666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 1692SN/A} 1702SN/A 1718706Sandreas.hansson@arm.comvoid 1728706Sandreas.hansson@arm.comSystem::init() 1738706Sandreas.hansson@arm.com{ 1748706Sandreas.hansson@arm.com // check that the system port is connected 1758706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 1768706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 1778706Sandreas.hansson@arm.com} 1788706Sandreas.hansson@arm.com 1799294Sandreas.hansson@arm.comBaseMasterPort& 1809294Sandreas.hansson@arm.comSystem::getMasterPort(const std::string &if_name, PortID idx) 1818703Sandreas.hansson@arm.com{ 1828703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 1838922Swilliam.wang@arm.com return _systemPort; 1848703Sandreas.hansson@arm.com} 1858703Sandreas.hansson@arm.com 1862901Ssaidi@eecs.umich.eduvoid 1874762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 1882901Ssaidi@eecs.umich.edu{ 1899342SAndreas.Sandberg@arm.com assert(getDrainState() == Drainable::Drained); 1902901Ssaidi@eecs.umich.edu memoryMode = mode; 1912901Ssaidi@eecs.umich.edu} 1922901Ssaidi@eecs.umich.edu 1933960Sgblack@eecs.umich.edubool System::breakpoint() 1943960Sgblack@eecs.umich.edu{ 1954095Sbinkertn@umich.edu if (remoteGDB.size()) 1964095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 1974095Sbinkertn@umich.edu return false; 1983960Sgblack@eecs.umich.edu} 1993960Sgblack@eecs.umich.edu 2007445Ssteve.reinhardt@amd.com/** 2017445Ssteve.reinhardt@amd.com * Setting rgdb_wait to a positive integer waits for a remote debugger to 2027445Ssteve.reinhardt@amd.com * connect to that context ID before continuing. This should really 2037445Ssteve.reinhardt@amd.com be a parameter on the CPU object or something... 2047445Ssteve.reinhardt@amd.com */ 2057445Ssteve.reinhardt@amd.comint rgdb_wait = -1; 2067445Ssteve.reinhardt@amd.com 207180SN/Aint 2085718Shsul@eecs.umich.eduSystem::registerThreadContext(ThreadContext *tc, int assigned) 2092SN/A{ 2105712Shsul@eecs.umich.edu int id; 2115718Shsul@eecs.umich.edu if (assigned == -1) { 2125718Shsul@eecs.umich.edu for (id = 0; id < threadContexts.size(); id++) { 2135718Shsul@eecs.umich.edu if (!threadContexts[id]) 2145718Shsul@eecs.umich.edu break; 2155718Shsul@eecs.umich.edu } 2165718Shsul@eecs.umich.edu 2175718Shsul@eecs.umich.edu if (threadContexts.size() <= id) 2185718Shsul@eecs.umich.edu threadContexts.resize(id + 1); 2195718Shsul@eecs.umich.edu } else { 2205718Shsul@eecs.umich.edu if (threadContexts.size() <= assigned) 2215718Shsul@eecs.umich.edu threadContexts.resize(assigned + 1); 2225718Shsul@eecs.umich.edu id = assigned; 2231806SN/A } 2241806SN/A 2252680Sktlim@umich.edu if (threadContexts[id]) 2265823Ssaidi@eecs.umich.edu fatal("Cannot have two CPUs with the same id (%d)\n", id); 2271806SN/A 2282680Sktlim@umich.edu threadContexts[id] = tc; 2295714Shsul@eecs.umich.edu _numContexts++; 2301070SN/A 2319850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 2325512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 2337445Ssteve.reinhardt@amd.com if (port) { 2344095Sbinkertn@umich.edu RemoteGDB *rgdb = new RemoteGDB(this, tc); 2355512SMichael.Adler@intel.com GDBListener *gdbl = new GDBListener(rgdb, port + id); 2364095Sbinkertn@umich.edu gdbl->listen(); 2377445Ssteve.reinhardt@amd.com 2384095Sbinkertn@umich.edu if (rgdb_wait != -1 && rgdb_wait == id) 2394095Sbinkertn@umich.edu gdbl->accept(); 2401070SN/A 2414095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2424095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2434095Sbinkertn@umich.edu } 2444095Sbinkertn@umich.edu 2454095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2461070SN/A } 2479850Sandreas.hansson@arm.com#endif 2481070SN/A 2497914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2507914SBrad.Beckmann@amd.com 2511806SN/A return id; 252180SN/A} 25375SN/A 2546029Ssteve.reinhardt@amd.comint 2556029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2566029Ssteve.reinhardt@amd.com{ 2576029Ssteve.reinhardt@amd.com int running = 0; 2586029Ssteve.reinhardt@amd.com for (int i = 0; i < _numContexts; ++i) { 2596029Ssteve.reinhardt@amd.com if (threadContexts[i]->status() != ThreadContext::Halted) 2606029Ssteve.reinhardt@amd.com ++running; 2616029Ssteve.reinhardt@amd.com } 2626029Ssteve.reinhardt@amd.com return running; 2636029Ssteve.reinhardt@amd.com} 2646029Ssteve.reinhardt@amd.com 265180SN/Avoid 2667733SAli.Saidi@ARM.comSystem::initState() 2671129SN/A{ 2688769Sgblack@eecs.umich.edu if (FullSystem) { 2699172Snilay@cs.wisc.edu for (int i = 0; i < threadContexts.size(); i++) 2708769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 2718799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 2728799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 2738799Sgblack@eecs.umich.edu /** 2748799Sgblack@eecs.umich.edu * Load the kernel code into memory 2758799Sgblack@eecs.umich.edu */ 2768885SAli.Saidi@ARM.com if (params()->kernel != "") { 27710282Sdam.sunwoo@arm.com if (params()->kernel_addr_check) { 27810282Sdam.sunwoo@arm.com // Validate kernel mapping before loading binary 27910282Sdam.sunwoo@arm.com if (!(isMemAddr((kernelStart & loadAddrMask) + 28010282Sdam.sunwoo@arm.com loadAddrOffset) && 28110282Sdam.sunwoo@arm.com isMemAddr((kernelEnd & loadAddrMask) + 28210282Sdam.sunwoo@arm.com loadAddrOffset))) { 28310282Sdam.sunwoo@arm.com fatal("Kernel is mapped to invalid location (not memory). " 28410282Sdam.sunwoo@arm.com "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n", 28510282Sdam.sunwoo@arm.com kernelStart, 28610282Sdam.sunwoo@arm.com kernelEnd, (kernelStart & loadAddrMask) + 28710282Sdam.sunwoo@arm.com loadAddrOffset, 28810282Sdam.sunwoo@arm.com (kernelEnd & loadAddrMask) + loadAddrOffset); 28910282Sdam.sunwoo@arm.com } 2909187SKrishnendra.Nathella@arm.com } 2918799Sgblack@eecs.umich.edu // Load program sections into memory 29210037SARM gem5 Developers kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset); 2938706Sandreas.hansson@arm.com 2948799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 2958799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 2968799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 2978799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 2988799Sgblack@eecs.umich.edu } 2998706Sandreas.hansson@arm.com } 3008706Sandreas.hansson@arm.com 3018706Sandreas.hansson@arm.com activeCpus.clear(); 3021129SN/A} 3031129SN/A 3041129SN/Avoid 3055713Shsul@eecs.umich.eduSystem::replaceThreadContext(ThreadContext *tc, int context_id) 306180SN/A{ 3075713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 3082680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 3095713Shsul@eecs.umich.edu context_id, threadContexts.size()); 310180SN/A } 311180SN/A 3125713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 3135713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 3145713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 3152SN/A} 3162SN/A 3172378SN/AAddr 3188601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 3192378SN/A{ 32010318Sandreas.hansson@arm.com Addr return_addr = pagePtr << PageShift; 3218601Ssteve.reinhardt@amd.com pagePtr += npages; 32210318Sandreas.hansson@arm.com if ((pagePtr << PageShift) > physmem.totalSize()) 3233162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3242378SN/A return return_addr; 3252378SN/A} 3265795Ssaidi@eecs.umich.edu 3275795Ssaidi@eecs.umich.eduAddr 3288931Sandreas.hansson@arm.comSystem::memSize() const 3295795Ssaidi@eecs.umich.edu{ 3308931Sandreas.hansson@arm.com return physmem.totalSize(); 3315795Ssaidi@eecs.umich.edu} 3325795Ssaidi@eecs.umich.edu 3335795Ssaidi@eecs.umich.eduAddr 3348931Sandreas.hansson@arm.comSystem::freeMemSize() const 3355795Ssaidi@eecs.umich.edu{ 33610318Sandreas.hansson@arm.com return physmem.totalSize() - (pagePtr << PageShift); 3375795Ssaidi@eecs.umich.edu} 3385795Ssaidi@eecs.umich.edu 3398460SAli.Saidi@ARM.combool 3408931Sandreas.hansson@arm.comSystem::isMemAddr(Addr addr) const 3418460SAli.Saidi@ARM.com{ 3428931Sandreas.hansson@arm.com return physmem.isMemAddr(addr); 3438460SAli.Saidi@ARM.com} 3448460SAli.Saidi@ARM.com 3459342SAndreas.Sandberg@arm.comunsigned int 3469342SAndreas.Sandberg@arm.comSystem::drain(DrainManager *dm) 3479342SAndreas.Sandberg@arm.com{ 3489342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 3499342SAndreas.Sandberg@arm.com return 0; 3509342SAndreas.Sandberg@arm.com} 3519342SAndreas.Sandberg@arm.com 3521070SN/Avoid 3539342SAndreas.Sandberg@arm.comSystem::drainResume() 3547897Shestness@cs.utexas.edu{ 3559342SAndreas.Sandberg@arm.com Drainable::drainResume(); 3567897Shestness@cs.utexas.edu totalNumInsts = 0; 3577897Shestness@cs.utexas.edu} 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.eduvoid 3601070SN/ASystem::serialize(ostream &os) 3611070SN/A{ 3628769Sgblack@eecs.umich.edu if (FullSystem) 3638769Sgblack@eecs.umich.edu kernelSymtab->serialize("kernel_symtab", os); 3647770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 3657770SAli.Saidi@ARM.com SERIALIZE_SCALAR(nextPID); 3669292Sandreas.hansson@arm.com serializeSymtab(os); 3679293Sandreas.hansson@arm.com 3689293Sandreas.hansson@arm.com // also serialize the memories in the system 3699293Sandreas.hansson@arm.com nameOut(os, csprintf("%s.physmem", name())); 3709293Sandreas.hansson@arm.com physmem.serialize(os); 3711070SN/A} 3721070SN/A 3731070SN/A 3741070SN/Avoid 3751070SN/ASystem::unserialize(Checkpoint *cp, const string §ion) 3761070SN/A{ 3778769Sgblack@eecs.umich.edu if (FullSystem) 3788769Sgblack@eecs.umich.edu kernelSymtab->unserialize("kernel_symtab", cp, section); 3797770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 3807770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(nextPID); 3819292Sandreas.hansson@arm.com unserializeSymtab(cp, section); 3829293Sandreas.hansson@arm.com 3839293Sandreas.hansson@arm.com // also unserialize the memories in the system 3849293Sandreas.hansson@arm.com physmem.unserialize(cp, csprintf("%s.physmem", name())); 3851070SN/A} 3862SN/A 3872SN/Avoid 3888666SPrakash.Ramrakhyani@arm.comSystem::regStats() 3898666SPrakash.Ramrakhyani@arm.com{ 3908666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 3918666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 3928666SPrakash.Ramrakhyani@arm.com stringstream namestr; 3938666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 3948666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 3958666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 3968666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 3978666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 3988666SPrakash.Ramrakhyani@arm.com } 3998666SPrakash.Ramrakhyani@arm.com} 4008666SPrakash.Ramrakhyani@arm.com 4018666SPrakash.Ramrakhyani@arm.comvoid 4028666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 4038666SPrakash.Ramrakhyani@arm.com{ 4048666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4058666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 4068666SPrakash.Ramrakhyani@arm.com return; 4078666SPrakash.Ramrakhyani@arm.com 4088666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 4098666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 4108666SPrakash.Ramrakhyani@arm.com 4118666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 4128666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 4138666SPrakash.Ramrakhyani@arm.com 4148666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 4158666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 4168666SPrakash.Ramrakhyani@arm.com} 4178666SPrakash.Ramrakhyani@arm.com 4188666SPrakash.Ramrakhyani@arm.comvoid 4192SN/ASystem::printSystems() 4202SN/A{ 4212SN/A vector<System *>::iterator i = systemList.begin(); 4222SN/A vector<System *>::iterator end = systemList.end(); 4232SN/A for (; i != end; ++i) { 4242SN/A System *sys = *i; 4252SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 4262SN/A } 4272SN/A} 4282SN/A 4292SN/Avoid 4302SN/AprintSystems() 4312SN/A{ 4322SN/A System::printSystems(); 4332SN/A} 4342SN/A 4358832SAli.Saidi@ARM.comMasterID 4368832SAli.Saidi@ARM.comSystem::getMasterId(std::string master_name) 4378832SAli.Saidi@ARM.com{ 4388832SAli.Saidi@ARM.com // strip off system name if the string starts with it 4399142Ssteve.reinhardt@amd.com if (startswith(master_name, name())) 4408832SAli.Saidi@ARM.com master_name = master_name.erase(0, name().size() + 1); 4418832SAli.Saidi@ARM.com 4428832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 4438832SAli.Saidi@ARM.com for (int i = 0; i < masterIds.size(); i++) { 4448832SAli.Saidi@ARM.com if (masterIds[i] == master_name) { 4458832SAli.Saidi@ARM.com return i; 4468832SAli.Saidi@ARM.com } 4478832SAli.Saidi@ARM.com } 4488832SAli.Saidi@ARM.com 4498986SAli.Saidi@ARM.com // Verify that the statistics haven't been enabled yet 4508986SAli.Saidi@ARM.com // Otherwise objects will have sized their stat buckets and 4518986SAli.Saidi@ARM.com // they will be too small 4528832SAli.Saidi@ARM.com 4538986SAli.Saidi@ARM.com if (Stats::enabled()) 4548832SAli.Saidi@ARM.com fatal("Can't request a masterId after regStats(). \ 4558832SAli.Saidi@ARM.com You must do so in init().\n"); 4568832SAli.Saidi@ARM.com 4578832SAli.Saidi@ARM.com masterIds.push_back(master_name); 4588832SAli.Saidi@ARM.com 4598832SAli.Saidi@ARM.com return masterIds.size() - 1; 4608832SAli.Saidi@ARM.com} 4618832SAli.Saidi@ARM.com 4628832SAli.Saidi@ARM.comstd::string 4638832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 4648832SAli.Saidi@ARM.com{ 4658832SAli.Saidi@ARM.com if (master_id >= masterIds.size()) 4668832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 4678832SAli.Saidi@ARM.com 4688832SAli.Saidi@ARM.com return masterIds[master_id]; 4698832SAli.Saidi@ARM.com} 4708832SAli.Saidi@ARM.com 4714762Snate@binkert.orgSystem * 4724762Snate@binkert.orgSystemParams::create() 4732424SN/A{ 4745530Snate@binkert.org return new System(this); 4752424SN/A} 476