sim_object.hh revision 2797:b5f26b4eacef 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32/* @file
33 * User Console Definitions
34 */
35
36#ifndef __SIM_OBJECT_HH__
37#define __SIM_OBJECT_HH__
38
39#include <map>
40#include <list>
41#include <vector>
42#include <iostream>
43
44#include "sim/serialize.hh"
45#include "sim/startup.hh"
46
47class BaseCPU;
48class Event;
49
50/*
51 * Abstract superclass for simulation objects.  Represents things that
52 * correspond to physical components and can be specified via the
53 * config file (CPUs, caches, etc.).
54 */
55class SimObject : public Serializable, protected StartupCallback
56{
57  public:
58    struct Params {
59        std::string name;
60    };
61
62    enum State {
63        Atomic,
64        Timing,
65        Quiescing,
66        QuiescedAtomic,
67        QuiescedTiming
68    };
69
70  protected:
71    Params *_params;
72    State state;
73
74    void changeState(State new_state) { state = new_state; }
75
76  public:
77    const Params *params() const { return _params; }
78
79    State getState() { return state; }
80
81  private:
82    typedef std::vector<SimObject *> SimObjectList;
83
84    // list of all instantiated simulation objects
85    static SimObjectList simObjectList;
86
87  public:
88    SimObject(Params *_params);
89    SimObject(const std::string &_name);
90
91    virtual ~SimObject() {}
92
93    virtual const std::string name() const { return params()->name; }
94
95    // initialization pass of all objects.
96    // Gets invoked after construction, before unserialize.
97    virtual void init();
98    virtual void connect();
99    static void initAll();
100    static void connectAll();
101
102    // register statistics for this object
103    virtual void regStats();
104    virtual void regFormulas();
105    virtual void resetStats();
106
107    // static: call reg_stats on all SimObjects
108    static void regAllStats();
109
110    // static: call resetStats on all SimObjects
111    static void resetAllStats();
112
113    // static: call nameOut() & serialize() on all SimObjects
114    static void serializeAll(std::ostream &);
115    static void unserializeAll(Checkpoint *cp);
116
117    // Methods to drain objects in order to take checkpoints
118    // Or switch from timing -> atomic memory model
119    // Quiesce returns true if the SimObject cannot quiesce immediately.
120    virtual bool quiesce(Event *quiesce_event);
121    virtual void resume();
122    virtual void setMemoryMode(State new_mode);
123    virtual void switchOut();
124    virtual void takeOverFrom(BaseCPU *cpu);
125
126#ifdef DEBUG
127  public:
128    bool doDebugBreak;
129    static void debugObjectBreak(const std::string &objs);
130#endif
131
132  public:
133    bool doRecordEvent;
134    void recordEvent(const std::string &stat);
135};
136
137#endif // __SIM_OBJECT_HH__
138